Global Patent Index - EP 0000480 B1

EP 0000480 B1 19810812 - METHOD OF PASSIVATING SEMICONDUCTOR ELEMENTS BY APPLYING A SILICON LAYER

Title (en)

METHOD OF PASSIVATING SEMICONDUCTOR ELEMENTS BY APPLYING A SILICON LAYER

Publication

EP 0000480 B1 19810812 (DE)

Application

EP 78100268 A 19780628

Priority

DE 2730367 A 19770705

Abstract (en)

[origin: CA1111149A] The present invention relates to a process for passivating the surfaces of semiconductor elements. Silicon layers which are vapourdeposited on the surface of semiconductor elements have the effect of a permanent stability on the characteristic curves of the semiconductor element. These silicon layers are annealed, in order to reduce the inverse currents. This effects a permanent lowering of the inverse-current level. This invention may be used on all semiconductor elements.

IPC 1-7

H01L 21/56

IPC 8 full level

H01L 21/203 (2006.01); H01L 21/56 (2006.01); H01L 21/314 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 29/74 (2006.01)

CPC (source: EP US)

H01L 21/56 (2013.01 - EP US); H01L 23/298 (2013.01 - EP US); H01L 23/3171 (2013.01 - EP US); H01L 23/3192 (2013.01 - EP US); H01L 2924/0002 (2013.01 - EP US); Y10S 438/958 (2013.01 - EP US)

C-Set (source: EP US)

H01L 2924/0002 + H01L 2924/00

Designated contracting state (EPC)

CH FR SE

DOCDB simple family (publication)

EP 0000480 A1 19790207; EP 0000480 B1 19810812; CA 1111149 A 19811020; DE 2730367 A1 19790118; DE 2730367 C2 19880114; GB 1587030 A 19810325; IT 1096857 B 19850826; IT 7825181 A0 19780630; JP S5417672 A 19790209; JP S6158976 B2 19861213; US 4322452 A 19820330

DOCDB simple family (application)

EP 78100268 A 19780628; CA 306759 A 19780704; DE 2730367 A 19770705; GB 2222978 A 19780525; IT 2518178 A 19780630; JP 8187078 A 19780705; US 17875080 A 19800818