Title (en)

DECODER CIRCUIT

Publication

EP 0035326 A3 19810923 (EN)

Application

EP 81300487 A 19810205

Priority

JP 1457680 A 19800208

Abstract (en)

[origin: US4369503A] A decoder circuit which receives a plurality of address signals and selects one of the nxm word lines for driving a semiconductor memory device. The decoder circuit includes a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level. The decoder circuit also includes a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level. The decoder circuit additionally includes nxm coupling circuits each of which receives one output from the high level selection circuit and one output from the low level selection circuit and which corresponds to one of the nxm word lines. Each of the coupling circuit selects the corresponding word line when the high level output from the high level selection circuit and the low level output from the low level selection circuit are simultaneously applied to the coupling circuit.

IPC 1-7

G11C 8/00; G11C 11/40; H03K 13/25

IPC 8 full level

G11C 11/413 (2006.01); G11C 8/10 (2006.01); G11C 8/12 (2006.01); G11C 11/415 (2006.01); H03M 7/00 (2006.01)

CPC (source: EP US)

G11C 8/10 (2013.01 - EP US); G11C 8/12 (2013.01 - EP US); G11C 11/415 (2013.01 - EP US); H03M 7/005 (2013.01 - EP US)

Citation (search report)

• [X] US 3736574 A 19730529 - GERSBACH J
• US 4007451 A 19770208 - HEUBER KLAUS, et al
• [P] EP 0019988 A1 19801210 - FUJITSU LTD [JP]
• [P] DE 2904457 A1 19800807 - SIEMENS AG
• [E] EP 0024894 A1 19810311 - FUJITSU LTD [JP]
• [A] US 4027285 A 19770531 - MILLHOLLAN MICHAEL S, et al
• [A] DE 2658523 A1 19780629 - SIEMENS AG
• IEEE Transactions on Electron Devices, Vol. ED-26, No. 6, June 1979, pages 886-892 New York, U.S.A. K. KAWARADA et al.: "A 4K-Bit Static I2L Memory" * pages 889-890, paragraph "D. New Decoder Circuit"; figures 6,7 *
• IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 5, October 1979, pages 850-854 New York, U.S.A. H. GLOCK et al.: "An ECL 100K-Compatible 1024 X 4 Bit RAM with 15 ns Access Time" * pages 851-852, paragraph "F Address Decoder"; figures 4,5
• IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 3, June 1980, pages 306-310 New York, U.S.A. H. ERNST et al.: "A High-Speed ECL 100K Compatible 64 X 4 Bit RAM with 6 ns Access Time" * figure 2 *
• Intel Data Sheet, December 1970, 15 pages, Intel Editor Mountain View, U.S.A. "Partially Decoded Ramdom Access 265 Bit Bipolar Memory (3102) and Binary Decoder-Driver (3202)" * pages 1,10 *
• IEEE International Solid-State Circuits Conference, 16th February 1978, pages 154-155 New York, U.S.A. P.M. QUINN et al.: "A 16K x 113L Dynamic RAM"
• IEEE Journal of Solid-State Circuits, Vol. SC-13, No. 5, October 1978, Pages 656-663 New York, U.S.A. K. KAWARADA et al.: "A Fast 7.5 ns Access IK-Bit RAM for Cache-Memory Systems"

Designated contracting state (EPC)

DE FR GB NL

DOCDB simple family (publication)

US 4369503 A 19830118; CA 1150838 A 19830726; EP 0035326 A2 19810909; EP 0035326 A3 19810923; IE 51987 B1 19870513; IE 810237 L 19810808; JP S56112122 A 19810904; JP S6261177 B2 19871219

DOCDB simple family (application)

US 23200881 A 19810206; CA 370290 A 19810206; EP 81300487 A 19810205; IE 23781 A 19810206; JP 1457680 A 19800208