EP 0039412 A3 19841010 - HIGH DENSITY MEMORY SYSTEM
Title (en)
HIGH DENSITY MEMORY SYSTEM
Publication
Application
Priority
US 14689780 A 19800505
Abstract (en)
[origin: EP0039412A2] In a multiprocessor system (2), a controllable cache store (18) interface to a shared disk memory (24) employs a plurality of storage partitions whose access is interleaved in a time domain multiplexed manner on a common bus (16) with the shared disk to enable high speed sharing of the disk storage by all of the processors (4, 6, 8). The communication between each processor and its corresponding cache memory partition can be overlapped with each other and with accesses between the cache memory (18) and the commonly shared disk memory (24). The addressable cache memory feature overcomes the latency delay which inherently occurs in seeking the beginning of a region to be accessed on the disk drive mass storage (24).
IPC 1-7
IPC 8 full level
G06F 3/06 (2006.01); G06F 12/08 (2006.01); G06F 13/28 (2006.01)
CPC (source: EP US)
G06F 12/084 (2013.01 - EP US); G06F 12/0871 (2013.01 - EP US); G06F 13/282 (2013.01 - EP US); G06F 2212/312 (2013.01 - EP US)
Citation (search report)
- [Y] US 4070706 A 19780124 - SCHEUNEMAN JAMES HERMAN
- [Y] US 4080651 A 19780321 - CRONSHAW DAVID, et al
- [Y] US 3546680 A 19701208 - BAHRS DAVID L, et al
- [Y] US 4181933 A 19800101 - BENYSEK BRUCE M [US]
- [A] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 20, no. 10, March 1978, pages 4226-4229, New York, US; R.P. FLETCHER: "System utilizing low cost control store backing memory"
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0039412 A2 19811111; EP 0039412 A3 19841010; EP 0039412 B1 19880727; BR 8102741 A 19820126; DE 3176824 D1 19880901; JP S56159888 A 19811209; JP S609298 B2 19850309; US 4371929 A 19830201
DOCDB simple family (application)
EP 81102500 A 19810402; BR 8102741 A 19810505; DE 3176824 T 19810402; JP 4568281 A 19810330; US 14689780 A 19800505