EP 0071494 B1 19860528 - METHOD OF MAKING INTEGRATED BIPOLAR TRANSISTORS OF VERY SMALL DIMENSIONS
Title (en)
METHOD OF MAKING INTEGRATED BIPOLAR TRANSISTORS OF VERY SMALL DIMENSIONS
Publication
Application
Priority
FR 8112604 A 19810626
Abstract (en)
[origin: US4481706A] A process is provided for manufacturing bi-polar transistors integrated on silicon. To form transistors of very small dimensions, a layer of polycrystalline silicon is deposited (after a localized oxidization step) which is etched and which is doped so as to serve as doping source for P+ extrinsic base regions of the transistor. After doping of the P intrinsic base, the oxide and/or nitride is then deposited at low pressure which is implanted with an impurity facilitating dissolution thereof. On the vertical walls of the polycrystalline silicon around the base, the nitride is not dissolved. Elsewhere it is easily dissolved. Advantage is taken of the oxide or nitride thickness which remains to form by diffusion of an N+ emitter region which will not extend laterally as far as the P+ type extrinsic base but which will allow to remain an intrinsic base of very small thickness. The emitter diffusion may take place through a second polycrystalline silicon layer.
IPC 1-7
IPC 8 full level
H01L 21/033 (2006.01); H01L 21/331 (2006.01); H01L 29/41 (2006.01)
CPC (source: EP US)
H01L 21/033 (2013.01 - EP US); H01L 29/41 (2013.01 - EP US); H01L 29/66272 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
FR 2508704 A1 19821231; FR 2508704 B1 19850607; DE 3271346 D1 19860703; EP 0071494 A1 19830209; EP 0071494 B1 19860528; US 4481706 A 19841113
DOCDB simple family (application)
FR 8112604 A 19810626; DE 3271346 T 19820624; EP 82401158 A 19820624; US 39236682 A 19820625