EP 0082980 B1 19860528 - SIGNAL TRANSFER ARRANGEMENT USING A BUS AS A STORAGE DEVICE
Title (en)
SIGNAL TRANSFER ARRANGEMENT USING A BUS AS A STORAGE DEVICE
Publication
Application
Priority
US 33418581 A 19811224
Abstract (en)
[origin: EP0082980A1] The signal transfer mechanism includes a plural-bit data bus (16) formed on an integrated circuit chip for transferring plural-bit binary data signals between plural-bit signal source registers (17, 18, 19, 26, 32, 35) and plural-bit signal destination registers (17, 18, 19, 26, 31, 32, 35) formed on the integrated circuit chip, and which are coupled to the plural-bit data bus (16) for respectively supplying plural-bit data signals to and receiving plural-bit data signals from the bus and a processor control unit (14) enabling one of the signal source register to put a plural-bit data signal onto the data bus (16) during a first processor control cycle and enabling one of the signal destination registers to take in this plural-bit data signal from the bus during a second and different processor control cycle. The inherent capacitance of the plural-bit data bus serves to store the plural-bit data signal during the first and second and any intervening processor control cycles.
IPC 1-7
IPC 8 full level
G06F 7/00 (2006.01); G06F 9/30 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01)
CPC (source: EP US)
G06F 13/4077 (2013.01 - EP US); G06F 15/7864 (2013.01 - EP US); Y02D 10/00 (2017.12 - EP US)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0082980 A1 19830706; EP 0082980 B1 19860528; CA 1180456 A 19850102; DE 3271462 D1 19860703; JP H0218498 B2 19900425; JP S58114154 A 19830707; MX 157488 A 19881125; MY 8800159 A 19881231; US 4567561 A 19860128
DOCDB simple family (application)
EP 82111122 A 19821202; CA 417165 A 19821207; DE 3271462 T 19821202; JP 22220182 A 19821220; MX 19547482 A 19821207; MY 8800159 A 19881230; US 33418581 A 19811224