EP 0088815 B1 19851218 - ELECTRICALLY ERASABLE MEMORY MATRIX (EEPROM)
Title (en)
ELECTRICALLY ERASABLE MEMORY MATRIX (EEPROM)
Publication
Application
Priority
EP 82102142 A 19820317
Abstract (en)
[origin: US4527256A] EEPROM showing storage cells comprising a tunnel injector which at the one hand is connected to a first bit line by means of the source-drain-line of a floating gate FET and at the other hand to a second bit line by means of the source-drain-line of a selection FET. Interferences between addressed groups and not addressed groups of storage cells during writing are eliminated by means of connection of the first bitline of the not addressed groups via the source-drain-lines of a depletion type FET and an enhancement FET to ground.
IPC 1-7
IPC 8 full level
G11C 29/00 (2006.01); G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 17/00 (2006.01); G11C 29/04 (2006.01); H01L 21/8247 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01)
CPC (source: EP US)
G11C 16/0433 (2013.01 - EP US); G11C 16/08 (2013.01 - EP US); G11C 16/10 (2013.01 - EP US); G11C 16/24 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 0088815 A1 19830921; EP 0088815 B1 19851218; DE 3267974 D1 19860130; JP H0234120 B2 19900801; JP S58171799 A 19831008; US 4527256 A 19850702
DOCDB simple family (application)
EP 82102142 A 19820317; DE 3267974 T 19820317; JP 4526583 A 19830317; US 47075983 A 19830228