EP 0099135 A3 19851023 - DYNAMIC GATE ARRAY WHEREBY AN ASSEMBLY OF GATES IS SIMULATED BY LOGIC OPERATIONS ON VARIABLES SELECTED ACCORDING TO THE GATES
Title (en)
DYNAMIC GATE ARRAY WHEREBY AN ASSEMBLY OF GATES IS SIMULATED BY LOGIC OPERATIONS ON VARIABLES SELECTED ACCORDING TO THE GATES
Publication
Application
Priority
JP 12387082 A 19820716
Abstract (en)
[origin: US4541071A] A gate assembly is simulated as logic groups, which are successively checked in steps for input signals of the respective logic groups to provide output signals thereof. A decode memory (24) is preliminarily loaded with decoding patterns. A pair of decoding patterns define a pair of variable sets which are preliminarily decided for each gate as regards a logic signal pair of each logic group input signal. In a gate memory unit (25), the variable pair is subjected to a logic operation decided for the gate to provide a logic signal of the logic group output signal. At first, a register set (15) is loaded with an input signal of the assembly. Later, the register set is loaded with the output signal of each logic group, which output signal is used in a next succeeding step as the input signal of another logic group. Preferably, each logic group input signal is given by eight logic signals. In this event, each logic signal may be given as a permutation of logic one and/or zero states, sixteen in number.
IPC 1-7
IPC 8 full level
G06F 7/00 (2006.01); G06F 7/76 (2006.01); G06F 17/50 (2006.01); H03K 19/173 (2006.01); H03K 19/177 (2006.01)
CPC (source: EP US)
G06F 7/76 (2013.01 - EP US); G06F 30/33 (2020.01 - EP US); H03K 19/1733 (2013.01 - EP US); H03K 19/17704 (2013.01 - EP US)
Citation (search report)
- [A] US 3700868 A 19721024 - SILVERTSON WILFORD E JR
- [A] FR 1475932 A 19670407 - TELEFUNKEN PATENT
- [A] ELECTRONICS LETTERS, vol. 2, no. 8, August 1966, pages 321-322, Hitchin, Herts., GB; L. ALEKSANDER: "Self-adaptive universal logic circuits"
- [A] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 17, no. 9, February 1975, pages 2720-2721, New York, US; M.T. LAAKSO et al.: "Boolean function synthesizer"
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
US 4541071 A 19850910; DE 3379858 D1 19890615; EP 0099135 A2 19840125; EP 0099135 A3 19851023; EP 0099135 B1 19890510; JP H0230056 B2 19900704; JP S5916050 A 19840127
DOCDB simple family (application)
US 51490083 A 19830718; DE 3379858 T 19830718; EP 83107041 A 19830718; JP 12387082 A 19820716