EP 0120721 B1 19870513 - WORD MEMORY WITH AN ADDRESS TRANSCODING CIRCUIT
Title (en)
WORD MEMORY WITH AN ADDRESS TRANSCODING CIRCUIT
Publication
Application
Priority
FR 8301544 A 19830201
Abstract (en)
[origin: US4586024A] Word store equipped with an address code conversion circuit making it possible to obtain AxB words, A and B not being powers of two. The code conversion circuit is in two parts CTA(X) and CTA(Y), allocated respectively to the code conversion of two addresses X and Y. The first part CTA(X) comprises a multiplexer M(X), which multiplexes the r most significant bits of X with the determined logic level. The second part CTA(Y) comprises a multiplexer M(Y), which multiplexes the r most significant bits of Y (with the exception of the most significant bit) with the r most significant bits of X. The multiplexers are controlled by the most significant bit of one of the addresses. Application to the formation of stores, particularly for graphic or alphanumeric display screens.
IPC 1-7
IPC 8 full level
G06F 12/00 (2006.01); G11C 8/00 (2006.01); G11C 8/02 (2006.01)
CPC (source: EP US)
G11C 8/00 (2013.01 - EP US)
Designated contracting state (EPC)
CH DE GB IT LI NL SE
DOCDB simple family (publication)
FR 2540277 A1 19840803; FR 2540277 B1 19850322; CA 1216954 A 19870120; DE 3463702 D1 19870619; EP 0120721 A1 19841003; EP 0120721 B1 19870513; JP S59146492 A 19840822; US 4586024 A 19860429
DOCDB simple family (application)
FR 8301544 A 19830201; CA 446408 A 19840131; DE 3463702 T 19840125; EP 84400165 A 19840125; JP 1692884 A 19840201; US 57490384 A 19840130