EP 0136819 A2 19850410 - Semiconductor memory.
Title (en)
Semiconductor memory.
Title (de)
Halbleiterspeicher.
Title (fr)
Mémoire semi-conductrice.
Publication
Application
Priority
JP 16183883 A 19830905
Abstract (en)
A semiconductor memory has a plurality of data lines (Y0 to Y3), a plurality of word lines (X0 to X3) which are arranged so as to intersect the plurality of data lines (Y0 to Y3), and a plurality of memory cells (MC) which are provided at intersection points of the plurality of data lines (Y0 to Y3) and the plurality of word lines (X0 to X3). A row decoder (3) selects at least one of the plurality of word lines (X0 to X3), and a column decoder (4) generates a signal for connecting one of the plurality of data lines (Y0 to Y3) to an input/output line I/O. A plurality of wiring leads (P) are formed of a conductor layer different from conductor layers forming the plurality of data lines (Y0 to Y3) and the plurality of word lines X0 to X3) are arranged so as to intersect the plurality of data lines (Y0 to Y3). In this way the area of the semiconductor chip 1, on which the memory is formed, may be reduced.
IPC 1-7
IPC 8 full level
G11C 11/413 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01); G11C 11/401 (2006.01); G11C 11/41 (2006.01); H01L 21/822 (2006.01); H01L 21/8242 (2006.01); H01L 27/04 (2006.01); H01L 27/10 (2006.01); H01L 27/108 (2006.01)
CPC (source: EP KR)
G11C 5/025 (2013.01 - EP); G11C 5/063 (2013.01 - EP); G11C 7/10 (2013.01 - EP); G11C 8/12 (2013.01 - EP); G11C 11/34 (2013.01 - KR); H10B 12/30 (2023.02 - EP)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0136819 A2 19850410; EP 0136819 A3 19870520; JP S6054471 A 19850328; KR 850002635 A 19850515
DOCDB simple family (application)
EP 84305933 A 19840830; JP 16183883 A 19830905; KR 840005421 A 19840904