Title (en)

PIPELINE CONTROL SYSTEM

Publication

EP 0163740 B1 19890510 (EN)

Application

EP 84904162 A 19841108

Priority

• JP 21202183 A 19831111
• JP 22562383 A 19831130

Abstract (en)

[origin: WO8502279A1] The following two address registers are provided independently of each other; an instruction address register unit I for reading out instructions, and an instruction address register unit II for indicating the address of an instruction being executed in a pipeline. The address of a branch instruction is held in the instruction address register unit II until the instruction has left the pipeline. The arrangement is such that it is possible to renew the contents of the instruction address register unit I at the moment when the route to be taken is determined according to the branch instruction, thereby minimizing delays involved in the operation of reading out the 8-bite previous instruction at the branch destination.

IPC 1-7

G06F 9/38

IPC 8 full level

G06F 9/32 (2006.01); G06F 9/38 (2006.01)

CPC (source: EP US)

G06F 9/321 (2013.01 - EP US); G06F 9/3804 (2013.01 - EP US)

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

WO 8502279 A1 19850523; AU 3612284 A 19850627; AU 560378 B2 19870402; BR 8407165 A 19851008; DE 3478157 D1 19890615; EP 0163740 A1 19851211; EP 0163740 A4 19860415; EP 0163740 B1 19890510; US 4802113 A 19890131

DOCDB simple family (application)

JP 8400535 W 19841108; AU 3612284 A 19841108; BR 8407165 A 19841108; DE 3478157 T 19841108; EP 84904162 A 19841108; US 75866585 A 19850625