EP 0166923 A2 19860108 - High performance bipolar transistor having a lightly doped guard ring disposed between the emitter and the extrinsic base region.
Title (en)
High performance bipolar transistor having a lightly doped guard ring disposed between the emitter and the extrinsic base region.
Title (de)
Hochleistungsbipolartransistor mit einem zwischen dem Emitter und der Extrinsic-Basiszone angeordneten leicht dotierten Schutzring.
Title (fr)
Transistor bipolaire de haute performance à anneau de garde à dopage léger disposé entre l'émetteur et la région de base extrinsèque.
Publication
Application
Priority
US 62627984 A 19840629
Abstract (en)
The present invention relates to a novel semiconductor device, such for example, an NPN bipolar transistor including a standard highly doped N<+> emitter (28) separated on its sidewalls fom the P<+> extrinsic base region (29) (base contact reach through) by a guard ring shaped region (30) having a significantly lower impurity concentration than the emitter (e.g. N<->). Said region (30) is located beneath an insulating spacer (25). The initial steps of the process are basically standard. The extrinsic base (29) is formed from a boron doped polysilicon contact region (16). The N<+> emitter region (28) is self aligned with the P<+> polysilicon contact region (16), and remains separated thereof by said N<-> region (30). The N<+> emitter (28) is formed either using ion implantation techniques or a doped emitter polysilicon contact region. However, according to the teachings of the present invention, the intrinsic base (22) of the transistor is formed in situ, by a low dose low energy P type ion implantation through a mask, made with its concentration peak below the device surface. Subsequently, an intermediate N<-> region is formed by implanting N type impurities through the same mask just to convert superficially the conductivity of the top surface above the P intrinsic base into N<-> type. The N<+> emitter may be then formed in such a way it is separated from the extrinsic base by a guard ring shaped portion (30) of said lightly doped intermediate N<-> region. The transistor thus formed will have a controllable narrow base width and optimized concentration, and will exhibit desired low external resistance through the extrinsic base region. Both factors are essential to provide high speed and low power devices. In addition, this transistor has a significantly high beta factor (in the range of 150) with a limited modulation of said gain factor; it has also good Emitter-Base breakdown voltages (in the range of 6V). Lastly, it presents increased inverse beta which is a highly desirable factor for Merged Transistor Logic (MTL) applications.
IPC 1-7
IPC 8 full level
H01L 21/331 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/73 (2006.01); H01L 29/732 (2006.01)
CPC (source: EP)
H01L 29/0642 (2013.01); H01L 29/0804 (2013.01); H01L 29/7325 (2013.01)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0166923 A2 19860108; EP 0166923 A3 19870930; JP S6119171 A 19860128
DOCDB simple family (application)
EP 85105728 A 19850510; JP 10413085 A 19850517