EP 0167764 A3 19860305 - DYNAMIC RAM CELL
Title (en)
DYNAMIC RAM CELL
Publication
Application
Priority
- US 62066784 A 19840614
- US 62651284 A 19840629
Abstract (en)
[origin: EP0167764A2] A Dynamic Random Access Memory (DRAM) cell has a storage capacitor (3) disposed in a trench (5) formed in a semiconductor substrate (6). The substrate is heavily doped and forms the counterelectrode of the storage capacitor, and a heavily doped polycrystalline plug (4) disposed in the trench forms the other electrode. The DRAM cell includes an access transistor (8, 9, 10, 11) which is disposed adjacent the top of the storage capacitor, and source (8) of the access transistor is connected to the plug electrode (4).
IPC 1-7
IPC 8 full level
H01L 27/108 (2006.01); H01L 29/94 (2006.01)
CPC (source: EP)
H01L 29/945 (2013.01); H10B 12/373 (2023.02)
Citation (search report)
- [X] EP 0108390 A1 19840516 - HITACHI LTD [JP]
- [Y] US 4364075 A 19821214 - BOHR MARK T, et al
- [A] EP 0031490 A2 19810708 - IBM [US]
- [X] PATENTS ABSTRACTS OF JAPAN, vol. 8, no. 103 (E-244) [1540], 15th May 1984; & JP - A - 59 019 366 (HITACHI SEISAKUSHO K.K.) 31-01-1984
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0167764 A2 19860115; EP 0167764 A3 19860305; EP 0167764 B1 19890816; DE 3572422 D1 19890921
DOCDB simple family (application)
EP 85106321 A 19850523; DE 3572422 T 19850523