Title (en)

PARALLEL PROCESSING COMPUTER

Publication

EP 0186150 A3 19880622 (EN)

Application

EP 85116294 A 19851219

Priority

• JP 27089884 A 19841224
• JP 27306184 A 19841226

Abstract (en)

[origin: EP0186150A2] A plurality of operation units (1, 2, 3) are connected to one another. The operation units include a processor (1), a buffer memory (2), and a data transfer control circuit (3) connected between the processor (1) and the buffer memory (2) for controlling the data input-output with the buffer memories in the other of the operation units. The buffer memories (2) and the data transfer control circuits (3) are connected with one another by data buses (201, 202 and 310, 320), respectively.

IPC 1-7

G06F 15/16; G06F 15/06

IPC 8 full level

G06F 15/173 (2006.01); G06F 15/80 (2006.01)

CPC (source: EP KR US)

G06F 15/16 (2013.01 - KR); G06F 15/17337 (2013.01 - EP US); G06F 15/8015 (2013.01 - EP US)

Citation (search report)

• [X] DE 3214068 A1 19831020 - VMEI LENIN NIS [BG]
• [YP] US 4514807 A 19850430 - NOGI TATSUO [JP]
• [Y] US 4208714 A 19800617 - EKLUND MATS F [SE], et al
• [Y] EP 0092719 A1 19831102 - SIEMENS AG [DE]
• [Y] US 4065808 A 19771227 - SCHOMBERG HERMANN, et al
• [Y] GB 2072900 A 19811007 - INT COMPUTERS LTD
• [Y] PATENT ABSTRACTS OF JAPAN, vol. 6, no. 51 (P-108)[929], 6th April 1982; & JP-A-56 164 464 (TATSUO NOGI) 17-12-1981

Designated contracting state (EPC)

DE FR GB SE

DOCDB simple family (publication)

EP 0186150 A2 19860702; EP 0186150 A3 19880622; EP 0186150 B1 19911127; CN 1008017 B 19900516; CN 85109763 A 19860716; DE 3584767 D1 19920109; KR 860005302 A 19860721; KR 930009760 B1 19931009; US 4816993 A 19890328

DOCDB simple family (application)

EP 85116294 A 19851219; CN 85109763 A 19851223; DE 3584767 T 19851219; KR 850009782 A 19851224; US 81027885 A 19851218