Title (en)

AUTOMATIC TEST SYSTEM HAVING A "TRUE TESTER-PER-PIN" ARCHITECTURE

Publication

EP 0228332 A3 19880831 (EN)

Application

EP 86402838 A 19861217

Priority

US 81047685 A 19851218

Abstract (en)

[origin: EP0228332A2] A multichannel automatic test system for an electronic circuit utilizes a "true tester-per-pin" architecture; each channel of the tester operates as if it were an independent tester. Each channel of the tester has a memory circuit which stores instructions for operating that channel of the tester. Each of these memories is cycled to the next address to provide a new instruction for that channel, only when it is necessary to change the state of operation of that channel. Thus, the timing of the events on one channel are independent of the timing on the events of any other channel in the tester. The architecture permits the use of dynamic random access memory (DRAM) circuits and allows for backward looping in the test sequence through the use of a cache memory circuit in each channel. The instructions for operating each channel of the tester are context-dependent; that is, the present state of operation of that channel of the tester is utilized in interpreting the next instruction for that channel.

IPC 1-7

G01R 31/28

IPC 8 full level

G01R 31/3183 (2006.01); G01R 31/319 (2006.01); G06F 11/22 (2006.01); H05K 3/00 (2006.01)

CPC (source: EP)

G01R 31/31921 (2013.01); G01R 31/31922 (2013.01)

Citation (search report)

• [X] EP 0149048 A1 19850724 - IBM [US]
• [A] EP 0131349 A1 19850116 - HEWLETT PACKARD CO [US]
• [E] US 4656632 A 19870407 - JACKSON PHILIP [US]
• [A] PROCEEDINGS AUTOTESTCON '84, Washington, 5th-7th November 1984, pages 80-86, IEEE; P.C. JACKSON et al.: "Initial physical implementation Universal Pin Electronics"
• [A] PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE, 16th-18th October 1984, pages 471-480, IEEE, Philadelphia, US; P.C. JACKSON et al.: "Compaction technique Universal Pin Electronics"
• [A] ELECTRONICS INTERNATIONAL, vol. 54, no. 22, 3rd November 1981, pages 122-127, New York, US; G.C. GILLETTE: "Tester takes on VLSI with 264-K vectors behind its pins"

Designated contracting state (EPC)

DE FR GB IT NL

DOCDB simple family (publication)

EP 0228332 A2 19870708; EP 0228332 A3 19880831; EP 0228332 B1 19931215; CA 1251575 A 19890321; DE 3689414 D1 19940127; DE 3689414 T2 19940623; JP H07120300 B2 19951220; JP S62271026 A 19871125

DOCDB simple family (application)

EP 86402838 A 19861217; CA 525024 A 19861211; DE 3689414 T 19861217; JP 29504886 A 19861212