EP 0244628 B1 19901227 - SENSE AMPLIFIER FOR A SEMICONDUCTOR MEMORY DEVICE
Title (en)
SENSE AMPLIFIER FOR A SEMICONDUCTOR MEMORY DEVICE
Publication
Application
Priority
JP 7300286 A 19860331
Abstract (en)
[origin: EP0244628A1] In a sense amplifier, the first input terminal of the differential amplifier (26) is connected to a first MOS transistor (23) operating as a transfer gate, a first floating gate transistor (22) operating as a memory cell, and a first load (24). The gates of the first MOS transistor (23) and the first floating gate transistor (22) are respectively connected to the column-select line (BL) and the word line (WL). The second input terminal of the differential amplifier (26) is connected to a second load (28), a second MOS transistor (31) operating as a transfer gate, and a second floating gate transistor (32) operating as a dummy cell. The second load (28) has the same characteristics as the first load (24). The second load (28) is composed of first and second load elements (28A, 28B). The second floating gate transistor (32) is constantly supplied with power voltage. When a shift in the thre shold voltage of the first floating gate transistor (22) is monitored, the first load element (28A) of the second load (28) is disconnected from the input terminal of the differential amplifier (26), and only the second load element (28B) remains connected to the input terminal. The gate of the second MOS transistor (31) is supplied with the high potential. A gradually increasing potential is applied to the gates of the first MOS transistor (23) and the first floating gate transistor (22). The potential is detected when the data of the first floating gate transistor changes from "0" to "1".
IPC 1-7
IPC 8 full level
G11C 7/06 (2006.01); G11C 16/12 (2006.01); G11C 16/28 (2006.01); G11C 16/34 (2006.01); G11C 17/00 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01)
CPC (source: EP KR)
G11C 7/06 (2013.01 - EP); G11C 16/12 (2013.01 - EP); G11C 16/28 (2013.01 - EP); G11C 16/3454 (2013.01 - EP); G11C 16/3459 (2013.01 - EP); G11C 17/00 (2013.01 - KR)
Citation (examination)
IEEE Journal of Solid-State Circuits, vol SC-20, no 1, Feb 1985, New York (US) S Atsumi et al: "Fast programmable 256K Read Only Memory with On-Chip Test Circuits", pp 422-427
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0244628 A1 19871111; EP 0244628 B1 19901227; DE 3767022 D1 19910207; JP H0444360 B2 19920721; JP S62231500 A 19871012; KR 870009398 A 19871026; KR 910001185 B1 19910225
DOCDB simple family (application)
EP 87104661 A 19870330; DE 3767022 T 19870330; JP 7300286 A 19860331; KR 870003023 A 19870331