Global Patent Index - EP 0269370 A3

EP 0269370 A3 19910508 - MEMORY ACCESS CONTROLLER

Title (en)

MEMORY ACCESS CONTROLLER

Publication

EP 0269370 A3 19910508 (EN)

Application

EP 87310226 A 19871119

Priority

JP 27685986 A 19861121

Abstract (en)

[origin: EP0269370A2] A memory access controller for transferring information from a certain processing unit among a plurality of processing units to another processing unit. The controller enables any two processing units, respectively represented by ports P1,P2, to effect transmission and reception therebetween simply, and with a reduced time limitation at a high speed. The controller includes memory means (30) for the common use of a plurality of processing units; means (31,32) for setting a periodical access time interval of a predetermined length during which write and read operations in and from said memory means (30) may be undertaken; selection means (37) for successively selecting those processing units one at a time on the basis of a predetermined selection reference when the processing unit issues a write or read request; and means (38,39) for permitting the memory access controller to inform the processing unit of being in execution of the request from said processing unit.

IPC 1-7

G06F 15/16

IPC 8 full level

G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 13/18 (2006.01); G06F 13/38 (2006.01); G06F 15/16 (2006.01)

CPC (source: EP KR)

G06F 3/00 (2013.01 - KR); G06F 13/18 (2013.01 - EP)

Citation (search report)

Designated contracting state (EPC)

DE FR GB IT

DOCDB simple family (publication)

EP 0269370 A2 19880601; EP 0269370 A3 19910508; EP 0269370 B1 19960131; AU 598870 B2 19900705; AU 8144587 A 19880526; CA 1296808 C 19920303; DE 3751693 D1 19960314; DE 3751693 T2 19960926; JP S63132369 A 19880604; KR 880006592 A 19880723; KR 920003174 B1 19920423

DOCDB simple family (application)

EP 87310226 A 19871119; AU 8144587 A 19871120; CA 552321 A 19871120; DE 3751693 T 19871119; JP 27685986 A 19861121; KR 870013041 A 19871119