EP 0280369 B1 19930714 - DEVICE FOR PROVIDING ACCESS TO A COMMON CIRCUIT TO TWO SIGNAL PROCESSORS
Title (en)
DEVICE FOR PROVIDING ACCESS TO A COMMON CIRCUIT TO TWO SIGNAL PROCESSORS
Publication
Application
Priority
FR 8702659 A 19870227
Abstract (en)
[origin: US4872108A] A priority processor (1) and a non-priority processor (20) cooperatively access a common memory (30) by means of an address multiplexer (40) which memory and multiplexer are controlled by a control unit (60). The priority processor issues data strobe (DSSN), clock (CLK) and write control (WSN) signals to the control unit to which the non-polarity processor also issues various memory access request signals. By forming a preparation signal (DSSN=0), the priority processor, through the control unit, claims the memory for a memory access cycle if a prior memory access request by the non-priority processor occurred less than about a clock cycle earlier.
IPC 1-7
IPC 8 full level
G06F 15/16 (2006.01); G06F 9/52 (2006.01); G06F 13/18 (2006.01); G06F 15/177 (2006.01)
CPC (source: EP US)
G06F 13/18 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT SE
DOCDB simple family (publication)
EP 0280369 A1 19880831; EP 0280369 B1 19930714; DE 3882248 D1 19930819; DE 3882248 T2 19940203; FR 2611396 A1 19880902; FR 2611396 B1 19911011; JP S63228366 A 19880922; US 4872108 A 19891003
DOCDB simple family (application)
EP 88200302 A 19880219; DE 3882248 T 19880219; FR 8702659 A 19870227; JP 4570188 A 19880227; US 15981788 A 19880224