EP 0293588 B1 19931006 - PEDESTAL TRANSISTORS AND METHOD OF PRODUCTION THEREOF
Title (en)
PEDESTAL TRANSISTORS AND METHOD OF PRODUCTION THEREOF
Publication
Application
Priority
US 4834587 A 19870511
Abstract (en)
[origin: EP0293588A2] The present invention describes a method of producing MOS, Bipolar, or BiMOS pedestal transistors wherein the source, drain, and gate metals (57, 64) are in place prior to the source/drain diffusion (62) in a MOS transistor; and the emitter and base metals (57, 64) are in place before junction formation on the bipolar transistors. This is accomplished in MOS devices by a first blanket implantation of impurities into a first polysilicon layer (56) during processing and a second blanket implantation into a second polysilicon layer (63) subsequent to deposition of the silicide layers (57, 64). This is accomplished in bipolar devices by the above, or by blanket implantations subsequent to the deposition of the silicide layers (57, 64).
IPC 1-7
IPC 8 full level
H01L 21/225 (2006.01); H01L 21/331 (2006.01); H01L 21/336 (2006.01); H01L 21/60 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 29/73 (2006.01); H01L 29/732 (2006.01); H01L 29/78 (2006.01)
CPC (source: EP US)
H01L 21/2257 (2013.01 - EP US); H01L 21/76897 (2013.01 - EP US); H01L 21/8249 (2013.01 - EP US); H01L 29/66272 (2013.01 - EP US); H01L 29/66606 (2013.01 - EP US)
Citation (examination)
- EP 0170250 A2 19860205 - TOSHIBA KK [JP]
- EP 0215583 A2 19870325 - ADVANCED MICRO DEVICES INC [US]
- EP 0051500 A2 19820512 - FUJITSU LTD [JP]
- IBM Technical Disclosure Bulletin, vol. 27, no. 10A, March 1985, pp. 5790-5794
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
US 4728391 A 19880301; DE 3884674 D1 19931111; EP 0293588 A2 19881207; EP 0293588 A3 19890405; EP 0293588 B1 19931006; JP S63292680 A 19881129
DOCDB simple family (application)
US 4834587 A 19870511; DE 3884674 T 19880421; EP 88106384 A 19880421; JP 11063988 A 19880509