Global Patent Index - EP 0312154 A1

EP 0312154 A1 19890419 - A method of forming an interconnection between conductive levels.

Title (en)

A method of forming an interconnection between conductive levels.

Title (de)

Methode zur Ausbildung von Verbindungen zwischen leitenden Ebenen.

Title (fr)

Méthode pour former des interconnexions entre des niveaux conducteurs.

Publication

EP 0312154 A1 19890419 (EN)

Application

EP 88202184 A 19881003

Priority

GB 8724319 A 19871016

Abstract (en)

A method of forming an interconnection between conductive levels is described in which a first conductive level (4) is provided on a surface of a substrate body such as a semiconductor body (1) so that the first conductive level (4) has a contact area (10). Passivating material (6) is provided on the surface of the body (1) to cover the first conductive level (4) and the contact area (10) then exposed by opening in the passivating material (6) a window (9) larger than the contact area (10) so that there is a gap (11) between the periphery (9a) of the window (9) and a side wall (5a) of the first conductive level (4) bounding the contact area (10). After opening the window (9) material (13b) is provided in the gap (11). Preferably, the material is provided by applying and then solidifying a spin-on-glass and subsequently etching back the spin-on-glass to expose the contact area. A second conductive level (7) is then provided on the smoothed surface to smooth the surface between the periphery (9a) of the window (9) and the contact area (10) so that part of the second conductive level (7) contacts the area (10) within the window (9).

IPC 1-7

H01L 21/316; H01L 21/90

IPC 8 full level

H01L 23/522 (2006.01); H01L 21/316 (2006.01); H01L 21/768 (2006.01)

CPC (source: EP KR US)

H01L 21/02164 (2013.01 - EP KR US); H01L 21/02274 (2013.01 - EP KR US); H01L 21/02282 (2013.01 - EP KR US); H01L 21/28 (2013.01 - KR); H01L 21/316 (2016.02 - US); H01L 21/76804 (2013.01 - EP US)

Citation (search report)

  • [YD] US 4594606 A 19860610 - GOTO HIDETO [JP], et al
  • [A] US 4185294 A 19800122 - OHASHI YOSHIE [JP], et al
  • [A] EP 0002185 A1 19790613 - IBM [US]
  • [A] EP 0223637 A1 19870527 - BULL SA [FR]
  • [Y] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 3, August 1978, pages 1052-1053, New York, US; J. GNIEWEK et al.: "Dual insulators for planar multilevel interconnections"
  • [A] THIN SOLID FILMS, vol. 93, no. 3/4, 1982, pages 359-383, Elsevier Sequoia, NL; P.B. GHATE: "Metallization for very-large-scale integrated circuits"

Designated contracting state (EPC)

DE FR GB IT NL

DOCDB simple family (publication)

EP 0312154 A1 19890419; EP 0312154 B1 19940105; DE 3886882 D1 19940217; DE 3886882 T2 19940630; GB 2211348 A 19890628; GB 8724319 D0 19871118; JP 2578178 B2 19970205; JP H01129445 A 19890522; KR 0134783 B1 19980420; KR 890007387 A 19890619; US 4965226 A 19901023

DOCDB simple family (application)

EP 88202184 A 19881003; DE 3886882 T 19881003; GB 8724319 A 19871016; JP 25604588 A 19881013; KR 880013328 A 19881013; US 46556090 A 19900116