EP 0312672 A1 19890426 - Offset correction circuit for a sigma-delta coding device.
Title (en)
Offset correction circuit for a sigma-delta coding device.
Title (de)
Offset-Korrekturschaltung für eine Sigma-Delta-Kodierungsvorrichtung.
Title (fr)
Circuit de correction de décalage pour un dispositif de codage sigma-delta.
Publication
Application
Priority
EP 87480015 A 19871019
Abstract (en)
Offset correction circuit in a digital-to-analog coder (10) comprising a delta coder (18) providing a serial bit string at a high frequency F in response to digital words supplied at a low frequency f, and an analog integrator (22) providing an analog output signal (24) which is an analog representation of the digital words. The offset correction circuit avoids an offset to be introduced in the analog output of the integrator (22) when a PLO correction is taken to slow down or to speed up the clock controlling the input of the digital words. Such a circuit can be implemented by a state generator which provides a corrected pulse in place of the sigma-delta data which lasts half the duration of the offset.
IPC 1-7
IPC 8 full level
H03M 1/10 (2006.01); H03M 3/02 (2006.01); H04B 14/06 (2006.01)
CPC (source: EP US)
H03M 3/356 (2013.01 - EP US); H04B 14/062 (2013.01 - EP US); H03M 3/50 (2013.01 - EP US)
Citation (search report)
- [A] US 4209773 A 19800624 - EVERARD JOHN D [GB]
- [A] GB 2077539 A 19811216 - LICENTIA GMBH
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0312672 A1 19890426; EP 0312672 B1 19920722; DE 3780640 D1 19920827; DE 3780640 T2 19930311; JP H01122211 A 19890515; US 4897856 A 19900130
DOCDB simple family (application)
EP 87480015 A 19871019; DE 3780640 T 19871019; JP 20030888 A 19880812; US 25463288 A 19881007