EP 0319066 B1 19940202 - Bias and precharging circuit for a bit line of EPROM memory cells in CMOS technology.
Title (en)
Bias and precharging circuit for a bit line of EPROM memory cells in CMOS technology.
Title (de)
Vorspannungs- und Vorladungsschaltung für eine Bitzeile mit EPROM-Speicherzellen in CMOS-Technologie.
Title (fr)
Circuit de polyrisation et de précharge pour une ligne de bit de cellules de mémoire EPROM en technologie CMOS.
Publication
Application
Priority
IT 2282887 A 19871201
Abstract (en)
[origin: EP0319066A2] The bias and precharging circuit comprises a bias part (5) and a precharging part (6) of the bit line (1) together with a sensing amplifier (7) operating by comparison of the voltage of the bit line (1) and a dummy bit line (2). The precharging part (6) comprises means (21) for turning off the bias and precharging parts (5, 6) as soon as the sensing amplifier (7) has read the cell subjected to precharging. The bias part (5) comprises means (16) for amplifying the voltage unbalance produced by bias between the bit line (1) and the dummy bit line (2). It provides current-mirror means (13, 14, 15) to cause said voltage unbalance independently of the precharging part (6).
IPC 1-7
IPC 8 full level
G11C 16/06 (2006.01); G11C 16/24 (2006.01); G11C 17/18 (2006.01); G11C 17/00 (2006.01)
CPC (source: EP)
G11C 16/24 (2013.01)
Designated contracting state (EPC)
DE FR GB NL SE
DOCDB simple family (publication)
EP 0319066 A2 19890607; EP 0319066 A3 19900328; EP 0319066 B1 19940202; DE 3887658 D1 19940317; DE 3887658 T2 19940630; IT 1232974 B 19920311; IT 8722828 A0 19871201; JP H023190 A 19900108; JP H0758596 B2 19950621
DOCDB simple family (application)
EP 88202573 A 19881117; DE 3887658 T 19881117; IT 2282887 A 19871201; JP 30112788 A 19881130