EP 0320977 A2 19890621 - Method for manufacturing semiconductor devices having twin wells.
Title (en)
Method for manufacturing semiconductor devices having twin wells.
Title (de)
Verfahren zum Herstellen von Halbleiteranordnungen mit Doppelwannen.
Title (fr)
Procédé pour fabriquer des dispositifs semi-conducteurs comportant des puits jumeaux.
Publication
Application
Priority
JP 31864987 A 19871218
Abstract (en)
A method for manufacturing twin well type semiconductor devices includes the steps of forming a first layer (12, 13; 12, 13, 14) on a P-type silicon substrate (11), selectively removing part of the first layer (12, 13; 12, 13, 14) to expose a predetermined portion of the surface of the substrate (11), ion-implanting phosphorus to introduce the phosphorus into the surface area of the substrate (11) under the first layer (12, 13; 12, 13, 14) and into a portion of the substrate (11) deeper than the substrate surface area below the predetermined portion of the substrate surface, ion-implanting boron to introduce the boron into the surface area of the first layer (12, 13; 12, 13, 14) and the surface area under the predetermined portion of the substrate (11), removing the first layer (12, 13; 12, 13, 14), and effecting heat treatment to diffuse the introduced phosphorus and boron.
IPC 1-7
IPC 8 full level
H01L 29/73 (2006.01); H01L 21/331 (2006.01); H01L 21/8238 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 29/732 (2006.01); H01L 27/092 (2006.01)
CPC (source: EP KR US)
H01L 21/823892 (2013.01 - EP US); H01L 21/8249 (2013.01 - EP US); H01L 29/68 (2013.01 - KR); H01L 29/72 (2013.01 - KR); H01L 27/0928 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0320977 A2 19890621; EP 0320977 A3 19900214; JP H01161752 A 19890626; KR 890011097 A 19890812; KR 910009034 B1 19911028; US 4931406 A 19900605
DOCDB simple family (application)
EP 88121131 A 19881216; JP 31864987 A 19871218; KR 880016872 A 19881217; US 28213888 A 19881209