EP 0327115 B1 19930428 - SERIAL ACCESS MEMORY SYSTEM PROVIDED WITH IMPROVED CASCADE BUFFER CIRCUIT
Title (en)
SERIAL ACCESS MEMORY SYSTEM PROVIDED WITH IMPROVED CASCADE BUFFER CIRCUIT
Publication
Application
Priority
JP 2489388 A 19880204
Abstract (en)
[origin: EP0327115A1] A serial access memory device with the improved cascade buffer circuit (20') for controlling serial access operation which has a small number of external terminals (Cin, Cout, FL) is disclosed. The cascade buffer circuit (20') includes first and second external terminals (Cin, Cout), a first control circuit for enabling the memory device to perform write operation and read operation when the level at the first external terminal (Cin) rises or falls and when the level at the first external terminal (Cin) falls or rises, respectively and a second control circuit for operatively causing the second external terminal (Cout) rise or fall when the memory device completes write operation and causing the second external terminal (Cout) fall or rise when the memory device completes read operation, respectively.
IPC 1-7
IPC 8 full level
G06F 13/38 (2006.01); G06F 5/06 (2006.01); G06F 5/08 (2006.01); G06F 12/06 (2006.01); G11C 19/28 (2006.01)
CPC (source: EP US)
G06F 5/08 (2013.01 - EP US); G11C 19/28 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0327115 A1 19890809; EP 0327115 B1 19930428; DE 68906171 D1 19930603; DE 68906171 T2 19930805; JP 2764908 B2 19980611; JP H01200447 A 19890811; US 4922457 A 19900501
DOCDB simple family (application)
EP 89101943 A 19890203; DE 68906171 T 19890203; JP 2489388 A 19880204; US 30660789 A 19890206