EP 0329104 A3 19911023 - IMAGE SIGNAL PROCESSOR WITH NOISE ELIMINATION CIRCUIT
Title (en)
IMAGE SIGNAL PROCESSOR WITH NOISE ELIMINATION CIRCUIT
Publication
Application
Priority
JP 3451888 A 19880216
Abstract (en)
[origin: EP0329104A2] For improvement in high frequency response characteristics, a noise eliminating circuit (22) incorporated in an image signal processor has a delay line (26) coupled between an output node of a charge coupled device (21) and a ground node, and an emitter follower circuit (27) coupled at the base node thereof to the output node the the charge coupled device, and each electric image signal supplied from the charge coupled device is reflected from the ground node to introduce a delay therein and merged into the subsequent electric image signal to produce a noise eliminated electric image signal which is supplied to the emitter follower circuit, so that the noise eliminated electric image signal is amplified by the emitter follower circuit with a constant gain, because of a small time constant coupled to the base node of the emitter follower circuit.
IPC 1-7
IPC 8 full level
H04N 25/00 (2023.01)
CPC (source: EP US)
H04N 25/60 (2023.01 - EP US)
Citation (search report)
[A] IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-15, no. 3, June 1980, pages 373-375; R.J. KANSY: "Response of a correlated double sampling circuit to 1/fnoise
Designated contracting state (EPC)
DE FR GB NL
DOCDB simple family (publication)
EP 0329104 A2 19890823; EP 0329104 A3 19911023; EP 0329104 B1 19950111; DE 68920452 D1 19950223; DE 68920452 T2 19950831; JP H01208975 A 19890822; US 4941052 A 19900710
DOCDB simple family (application)
EP 89102587 A 19890215; DE 68920452 T 19890215; JP 3451888 A 19880216; US 31062089 A 19890215