Title (en)

NONVOLATILE SEMICONDUCTOR MEMORY

Publication

EP 0345791 A3 19920311 (EN)

Application

EP 89110412 A 19890608

Priority

JP 14205188 A 19880609

Abstract (en)

[origin: EP0345791A2] A memory cell array (MA) includes a matrix array of a plurality of memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23). These memory cells are nonvolatile transistors. The memory cells (MC00 to MC03, MC10 to MC13, MC20 to MC23, MC30 to MC33) which are arrayed in each row of the memory array (MM), are coupled with a plurality of word lines (WL0 to WL3). The word lines are selected by a row decoder (10) made up of a plurality of partial decoders (100 to 103). In this case, a constant voltage output circuit (20), which is provided at the outputs of the partial decoders 100 to 103) of the row decoder (10), outputs a constant voltage lower than a power source voltage to a corresponding word line of those word lines (WL0 to WL3) when the corresponding word line is selected by the outputs of the partial decoders (100 to 103).

IPC 1-7

G11C 17/00; G11C 8/00

IPC 8 full level

G11C 17/00 (2006.01); G11C 16/06 (2006.01); G11C 16/08 (2006.01)

CPC (source: EP KR US)

G11C 16/08 (2013.01 - EP US); G11C 17/00 (2013.01 - KR)

Citation (search report)

• [A] GB 2127642 A 19840411 - NEC CORP
• [A] US 4460981 A 19840717 - VAN BUSKIRK MICHAEL A [US], et al
• [A] EP 0211232 A2 19870225 - NEC CORP [JP]

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

EP 0345791 A2 19891213; EP 0345791 A3 19920311; JP H023187 A 19900108; KR 900000915 A 19900131; KR 910008693 B1 19911019; US 5018108 A 19910521

DOCDB simple family (application)

EP 89110412 A 19890608; JP 14205188 A 19880609; KR 890007941 A 19890609; US 36218089 A 19890606