EP 0349124 A3 19911218 - OPERAND SPECIFIER PROCESSING
Title (en)
OPERAND SPECIFIER PROCESSING
Publication
Application
Priority
US 21234888 A 19880627
Abstract (en)
[origin: EP0349124A2] A method of specifying the operands for a microcoded CPU employs a combination of a set of microinstruction routines for generic operand modes, along with hardware primitives for selecting various specific types of operand treatment. Decode of a machine-level instruction produces an entry point for the microstore to select one of the set of generic operand modes, and also decode of the instruction produces control bits that are used directly to select the specific operand type or use by the hardware primitives. In this way, branching is avoided in the microinstruction sequences for operand specifying, but yet the amount of microcode needed is a minimum.
IPC 1-7
IPC 8 full level
G06F 9/22 (2006.01); G06F 9/30 (2006.01); G06F 9/34 (2006.01)
CPC (source: EP US)
G06F 9/22 (2013.01 - EP US); G06F 9/3016 (2013.01 - EP US); G06F 9/34 (2013.01 - EP US)
Citation (search report)
- [E] EP 0325226 A2 19890726 - TOSHIBA KK [JP]
- [A] US 3958221 A 19760518 - SERRA JOHN J, et al
- [A] EP 0087785 A2 19830907 - HITACHI LTD [JP]
- [A] SYSTEMS AND COMPUTERS IN JAPAN, no. 3, May-June 1985, pages 19-28, Washington, DC, US; H. MATSUMOTO et al.: "A high-performance architecture for variable length instructions"
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0349124 A2 19900103; EP 0349124 A3 19911218; EP 0349124 B1 19961009; CA 1321652 C 19930824; DE 68927313 D1 19961114; DE 68927313 T2 19970507; JP 2840604 B2 19981224; JP H0296233 A 19900409; US 5500947 A 19960319
DOCDB simple family (application)
EP 89305430 A 19890530; CA 603886 A 19890626; DE 68927313 T 19890530; JP 16514189 A 19890627; US 26999194 A 19940701