EP 0377296 A3 19910911 - PROGRAMMABLE OPTION SELECTION AND PAGED MEMORY CACHE COHERENCY CONTROL
Title (en)
PROGRAMMABLE OPTION SELECTION AND PAGED MEMORY CACHE COHERENCY CONTROL
Publication
Application
Priority
US 29322189 A 19890104
Abstract (en)
[origin: EP0377296A2] A cache flush request circuit for a computer system which flushes (72) the cache controller when a circuit board is being configured (62,64,66, 68) or is responding (68,70) to an input/output write operation (50) is described. The flush operation can be disabled (56,58) for each circuit board location. A cache flush operation can also be directly requested (72,74,76,78,80).
IPC 1-7
IPC 8 full level
G06F 12/08 (2006.01)
CPC (source: EP US)
G06F 12/0835 (2013.01 - EP US)
Citation (search report)
- [A] MICROPROCESSORS & MICROSYSTEMS, vol. 12, no. 3, April 1988, pages 147-152; G. LAWS: "Multiprocessing on the Nubus using cache inhibited pages"
- [A] COMPUTER DESIGN, vol. 26, no. 14, August 1987, pages 89-94; W. VAN LOO: "Maximize performance by choosing best memory"
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 0377296 A2 19900711; EP 0377296 A3 19910911; EP 0377296 B1 19960228; CA 2005698 A1 19900704; DE 68925807 D1 19960404; DE 68925807 T2 19960905; US 5095428 A 19920310
DOCDB simple family (application)
EP 89313158 A 19891215; CA 2005698 A 19891215; DE 68925807 T 19891215; US 29322189 A 19890104