EP 0398244 A3 19920617 - DYNAMIC TYPE RANDOM-ACCES MEMORY
Title (en)
DYNAMIC TYPE RANDOM-ACCES MEMORY
Publication
Application
Priority
JP 12120989 A 19890515
Abstract (en)
[origin: EP0398244A2] This invention discloses a dynamic type random-access memory which includes a bit line pair, a memory cell array including a plurality of memory cells (MCi; i = 0 to 255), a bit line sense amplifier (NA, PA) which is enabled after data written in one of the plurality of memory cells (MCi; i = 0 to 255) is read out onto the bit line pair, and a charge transfer circuit (NT1, NT2) which is connected between the bit line pair and sense nodes (SN, SN) of the bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of the bit line sense amplifier (NA, PA) is started.
IPC 1-7
IPC 8 full level
G11C 11/409 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC (source: EP KR)
G11C 11/407 (2013.01 - KR); G11C 11/409 (2013.01 - EP); G11C 11/4091 (2013.01 - EP); G11C 11/4096 (2013.01 - EP)
Citation (search report)
- [Y] US 4112512 A 19780905 - ARZUBI LUIS MARIA, et al
- [X] IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. SC-13, no. 5, October 1978, NEW YORK US pages 607 - 610; WADA T. ET AL: 'A 150ns, 150mW, 64K Dynamic MOS RAM'
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0398244 A2 19901122; EP 0398244 A3 19920617; JP H02301097 A 19901213; KR 900019040 A 19901222
DOCDB simple family (application)
EP 90109122 A 19900515; JP 12120989 A 19890515; KR 900007092 A 19900515