EP 0398382 A3 19921014 - PIPELINE PROCESSOR AND PIPELINE PROCESSING METHOD FOR MICROPROCESSOR
Title (en)
PIPELINE PROCESSOR AND PIPELINE PROCESSING METHOD FOR MICROPROCESSOR
Publication
Application
Priority
JP 12453389 A 19890519
Abstract (en)
[origin: EP0398382A2] A pipeline processor adopted for a microprocessor executes pipeline processes. The pipeline processes comprise the steps of reading a machine language instruction; decoding the read instruction; generating an address according to the decoded instruction; reading operand data from a cache memory (27) according to the generated address; executing the instruction; and writing data into the cache memory (27). When the machine language instruction is a write instruction, the operand data reading step involves a process of searching the cache memory (27) for the address where data is to be written. A result of the search is held in flag memories. Thereafter, the data writing step involves a process of referring to the flag memories, and is completed in one machine cycle.
IPC 1-7
IPC 8 full level
G06F 9/38 (2006.01); G06F 12/08 (2006.01); G11C 8/00 (2006.01)
CPC (source: EP KR US)
G06F 9/38 (2013.01 - KR); G06F 9/3824 (2013.01 - EP US); G06F 9/3875 (2013.01 - EP US); G11C 8/00 (2013.01 - EP US)
Citation (search report)
- [A] WO 8704823 A1 19870813 - DIGITAL EQUIPMENT CORP [US]
- [A] GB 2200483 A 19880803 - NAT SEMICONDUCTOR CORP
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0398382 A2 19901122; EP 0398382 A3 19921014; EP 0398382 B1 19960925; DE 69028655 D1 19961031; DE 69028655 T2 19970306; JP H02304650 A 19901218; JP H077356 B2 19950130; KR 900018808 A 19901222; KR 930003401 B1 19930426; US 5197134 A 19930323
DOCDB simple family (application)
EP 90109595 A 19900521; DE 69028655 T 19900521; JP 12453389 A 19890519; KR 900007077 A 19900517; US 52577490 A 19900521