EP 0403990 A3 19910925 - HIGH RESOLUTION SAMPLE CLOCK GENERATOR WITH DEGLITCHER
Title (en)
HIGH RESOLUTION SAMPLE CLOCK GENERATOR WITH DEGLITCHER
Publication
Application
Priority
US 36947489 A 19890621
Abstract (en)
[origin: EP0403990A2] A digital controlled clock provides ultra fine resolution for a sampling clock signal for recovering data from a received signal, the phase jump of the sampling clock signal being determined the number of stages in a multiphase clock generator that generates a number of equally-spaced phase clock outputs based on a reference clock signal. Phase selection is performed through a very low overhead phase commutator in response to phase advance/retard inputs. A clock deglitcher matched to the stages of the ring oscillator eliminates spikes generated when the phase commutator switches.
IPC 1-7
IPC 8 full level
H03L 7/00 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01)
CPC (source: EP KR US)
H02H 9/00 (2013.01 - KR); H03L 7/0996 (2013.01 - EP US); H04L 7/0083 (2013.01 - EP US); H04L 7/0337 (2013.01 - EP US)
Citation (search report)
- [Y] US 4233525 A 19801111 - TAKAHASHI YUKIO, et al
- [E] EP 0380979 A2 19900808 - ASIX SYSTEMS CORP [US]
- [X] IBM TECHNICAL DISCLOSURE BULLETIN, vol. 30, no. 4, September 1988, pages 313-315, Armonk, New York, US; "Digital delay controlled oscillator"
Designated contracting state (EPC)
DE FR GB IT NL
DOCDB simple family (publication)
EP 0403990 A2 19901227; EP 0403990 A3 19910925; EP 0403990 B1 19960529; CA 2019347 A1 19901221; DE 69027152 D1 19960704; DE 69027152 T2 19970116; JP 3009186 B2 20000214; JP H03141723 A 19910617; KR 910002065 A 19910131; US 5018169 A 19910521
DOCDB simple family (application)
EP 90111405 A 19900616; CA 2019347 A 19900620; DE 69027152 T 19900616; JP 16147090 A 19900621; KR 900009067 A 19900620; US 36947489 A 19890621