EP 0431290 B1 19950621 - MOS switching circuit having gate enhanced lateral bipolar transistor.
Title (en)
MOS switching circuit having gate enhanced lateral bipolar transistor.
Title (de)
MOS-Schaltkreis mit einem Gate-optimierten lateralen bipolaren Transistor.
Title (fr)
Circuit de commutation MOS comportant un transistor bipolaire latéral perfectionné par une grille.
Publication
Application
Priority
US 44798489 A 19891208
Abstract (en)
[origin: EP0431290A2] Circuitry for implementing a gate enhanced lateral transistor (3l) to provide a circuit having a bipolar current driving capability and an FET channel voltage drop. The circuits provide switching of the lateral transistor by enabling both gate and base connections. The device is merged into an FET providing essentially no voltage drop across the collector-emitter connections permitting the collector to reach a full power supply voltage. <IMAGE>
IPC 1-7
IPC 8 full level
H01L 29/73 (2006.01); H01L 21/331 (2006.01); H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 27/07 (2006.01); H03K 17/04 (2006.01); H03K 17/567 (2006.01); H03K 19/08 (2006.01)
CPC (source: EP US)
H01L 27/0711 (2013.01 - EP US)
Citation (examination)
PATENT ABSTRACTS OF JAPAN, vol.11, no. 130, (E-502)(2577) 23 April 1987;& JP-A-61274512
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
US 4999518 A 19910312; DE 69020316 D1 19950727; DE 69020316 T2 19960208; EP 0431290 A2 19910612; EP 0431290 A3 19920129; EP 0431290 B1 19950621; JP H03190426 A 19910820
DOCDB simple family (application)
US 44798489 A 19891208; DE 69020316 T 19901020; EP 90120140 A 19901020; JP 31819090 A 19901126