Global Patent Index - EP 0431911 A3

EP 0431911 A3 19920603 - MEMORY CELL HAVING FLOATING GATE AND SEMICONDUCTOR MEMORY USING THE SAME

Title (en)

MEMORY CELL HAVING FLOATING GATE AND SEMICONDUCTOR MEMORY USING THE SAME

Publication

EP 0431911 A3 19920603 (EN)

Application

EP 90313184 A 19901205

Priority

JP 31837889 A 19891207

Abstract (en)

[origin: EP0431911A2] A memory cell (17) for storing data includes a first field effect transistor (Q12) having a source receiving a first voltage (VSE, Vcc), a floating gate, and a drain receiving data to be written into said memory cell and outputting said data, and a second field effect transistor (Q11) having a source receiving a second voltage (Vss), a floating gate connected to the floating gate of said first field effect transistor, and a drain connected to the drain of said first field effect transistor. The second field effect transistor has a conduction type opposite to that of said first field effect transistor. The memory cell also includes a capacitor (C11) which has a first terminal receiving a select signal for identifying said memory cell, and a second terminal connected to the floating gates of said first and second field effect transistors. The data is stored in the floating gates of said first and second field effect transistors. <IMAGE>

IPC 1-7

G11C 16/04

IPC 8 full level

G11C 17/00 (2006.01); G11C 16/04 (2006.01); G11C 29/00 (2006.01); H01L 21/82 (2006.01); H01L 21/8247 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); H10B 69/00 (2023.01)

CPC (source: EP KR US)

G11C 16/0441 (2013.01 - EP KR US); G11C 16/045 (2013.01 - EP US); G11C 16/10 (2013.01 - KR); G11C 16/26 (2013.01 - KR); G11C 16/30 (2013.01 - KR); G11C 29/789 (2013.01 - EP US); G11C 29/83 (2013.01 - EP US); H10B 41/00 (2023.02 - KR); G11C 2216/10 (2013.01 - EP US)

Citation (search report)

  • [X] US 4132904 A 19790102 - HARARI ELIYAHOU
  • [Y] US 4885719 A 19891205 - BRAHMBHATT DHAVAL J [US]
  • [Y] EP 0103043 A1 19840321 - ITT IND GMBH DEUTSCHE [DE], et al
  • [AE] US 5016217 A 19910514 - BRAHMBHATT DHAVAL J [US]
  • [A] EP 0254139 A2 19880127 - TOSHIBA KK [JP], et al
  • [A] WO 8906068 A1 19890629 - XICOR INC [US]
  • [X] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 13, no. 1, June 1970, NEW YORK US pages 263 - 264; KRICK: 'Complementary MNOS Electronically Alterable Read-only Memory'
  • [X] IEEE 1985 ELECTRONICOM vol. 3, 6 October 1985, TORONTO, ONTARIO, CA pages 590 - 593; SALEH ET AL: 'A Simulation of a Non-avalanche Injection Based CMOS EEPROM Memory Cell compatible with Scaling-down Trends'
  • [Y] WESTE, NEIL H E ET AL 'Principles of CMOS VLSI Design' October 1985 , ADDISON WESLEY , READING US
  • [Y] RCA TECHNICAL NOTES. no. 1185, 24 June 1977, PRINCETON US pages 1 - 4; MEDWIN ET AL: 'FACMOS EAROM'
  • [A] IEEE JOURNAL OF SOLID-STATE CIRCUITS. vol. 22, no. 5, October 1987, NEW YORK US pages 669 - 675; OHTSUKA ET AL: 'A 4-Mbit CMOS EPROM'
  • [A] INTEGRATION, THE VLSI JOURNAL. vol. 8, no. 2, November 1989, AMSTERDAM NL pages 189 - 199; SCHULTZ ET AL: 'A microprogrammable processor using single poly EPROM'
  • EDN ELECTRICAL DESIGN NEWS. vol. 32, no. 19, 17 September 1987, NEWTON, MASSACHUSETTS US pages 132 - 138; WRIGHT: 'High-speed EPROMS'

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

EP 0431911 A2 19910612; EP 0431911 A3 19920603; EP 0431911 B1 19960228; DE 69025561 D1 19960404; JP H03179780 A 19910805; KR 910013284 A 19910808; KR 950014091 B1 19951121; US 5404328 A 19950404

DOCDB simple family (application)

EP 90313184 A 19901205; DE 69025561 T 19901205; JP 31837889 A 19891207; KR 900020091 A 19901207; US 26235294 A 19940620