Global patent index - EP 0435404 B1

EP 0435404 B1 2000-10-25 - Differential input bicmos buffer-inverters and gates

Title (en)

Differential input bicmos buffer-inverters and gates

Title (de)

BiCMOS-Pufferinverter und Gatter mit differentielem Eingang

Title (fr)

Portes et tampons inverseurs biCMOS avec une entrée différentielle

Publication

EP 0435404 B1 (EN)

Application

EP 90203439 A

Priority

US 45821789 A

Abstract (en)

[origin: EP0435404A2] High speed and high drive BICMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor (120a) has a base receiving a noninverting input (Vin), a collector coupled to the high voltage rail (VHH), and an emitter coupled to the circuit output (Vout). In several embodiments, the second bipolar transistor (128a) has its collector coupled to the emitter of the first bipolar transistor (120a), its emitter coupled to ground, and its base coupled to the source of an nMOS transistor (122a) which is receiving the inverting input (Vin) at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor (120a) and the collector of the second bipolar transistor (128a) with the first bipolar transistor pulling up when when the input is low. Also, in several of the embodiments, the first bipolar transistor (120a) is coupleed to a pMOS device (126a) with the collector connected to the source, and the emitter connected to the drain. the gate of the pMOS device is coupled to the inverting input (Vin), sometimes via the emitter of another bipolar transistor having its base connected to the inverting input. the pMOS device (126a) acts to pull up the output voltage of the circuit from the voltage provided at the emitter of the first bipolar transistor (120a) to the voltage of the high voltage rail (VHH).

IPC 1-7 (main, further and additional classification)

H03K 19/094; H03K 19/0175

IPC 8 full level (invention and additional information)

H03K 17/567 (2006.01); H03K 17/00 (2006.01); H03K 19/0175 (2006.01); H03K 19/08 (2006.01); H03K 19/0944 (2006.01)

CPC (invention and additional information)

H03K 19/09448 (2013.01); H03K 19/017527 (2013.01)

Citation (examination)

EP 0209805 A2 19870128 - HITACHI LTD [JP]

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

EP 0435404 A2 19910703; EP 0435404 A3 19911127; EP 0435404 B1 20001025; DE 69033654 D1 20001130; DE 69033654 T2 20010510; JP 3117223 B2 20001211; JP H04280114 A 19921006; KR 100220112 B1 19990901

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