EP 0442474 A3 19920506 - APPARATUS AND METHOD FOR CONTROLLING CACHE MEMORY
Title (en)
APPARATUS AND METHOD FOR CONTROLLING CACHE MEMORY
Publication
Application
Priority
- JP 3305490 A 19900213
- JP 3305590 A 19900213
Abstract (en)
[origin: EP0442474A2] A cache memory control apparatus for controlling a virtual address cache memory includes a main storage provided with a table in which task codes of (m+n) bits are sequentially set with respect to tasks of 2<m+n> (m is 0 or a natural number and n is a natural number) selected from a plurality of tasks which can be executed by a processor. An index of a virtual address outputted from the processor is applied to a cache memory as a lower address thereof. An ID number of a task intended to be executed by the processor is set in a first register, and a task code (or a lower n-bits thereof) set in the table correspondingly to the ID number is applied to the cache memory from a second register as an upper address. Therefore, the cache memory is divided in accordance with the task code (or the lower n-bits thereof). In addition, in order to specify data for a task of the ID number in a divided area, an upper m-bits of the task code is stored in a tag memory together with a tag of the virtual address, and the tag of the virtual address outputted by the processor and the upper m-bits of the second register are compared with a tag read from the tag memory. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 12/08 (2006.01); G06F 12/0842 (2016.01); G06F 12/10 (2006.01); G06F 12/1045 (2016.01)
CPC (source: EP)
G06F 12/0842 (2013.01); G06F 12/1063 (2013.01)
Citation (search report)
- [X] GB 2045483 A 19801029 - HONEYWELL INC
- [A] FR 2621407 A1 19890407 - SUN MICROSYSTEMS INC [US]
- [Y] MOTOROLA TECHNICAL DEVELOPMENTS. vol. 6, no. 1, October 1986, SCHAUMBURG, ILLINOIS US page 30; MOYER ET AL: 'Provision of Internal Cache Status for External Cache Management'
- [X] PROCEEDINGS OF REAL-TIME SYSTEMS SYMPOSIUM 1989 December 1989, ASHINGTON, IEEE COMP. SOC PRESS; US pages 229 - 237; KIRK: 'SMART (Strategic Memory Allocation for Real-Time) Cache Design'
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0442474 A2 19910821; EP 0442474 A3 19920506; EP 0442474 B1 19970723; DE 69126898 D1 19970904; DE 69126898 T2 19980305
DOCDB simple family (application)
EP 91102021 A 19910213; DE 69126898 T 19910213