Title (en)

EFFECTIVE ADDRESS PRE-CALCULATION TYPE PIPELINED MICROPROCESSOR

Publication

EP 0443629 A3 19930728 (EN)

Application

EP 91102762 A 19910225

Priority

JP 4401890 A 19900223

Abstract (en)

[origin: EP0443629A2] An effective address pre-calculation type pipelined microprocessor comprises a register file which can be used for a base address for an operand address and an effective address calculation unit for calculating and generating an effective address of an operand prior to execution of an instruction, by using an register included in the register file as a base address register. A copy register is provided for selecting and holding either the calculated effective address or a modification amount added result obtained by adding a constant number to the calculated effective address, and a copy valid flag is provided for storing a history of a written condition of the copy register. When an auto-modification designation mode is detected, a calculated effective address or the modification amount added result is written to the copy register. A copy register identification code latch stores an identification code of a register which is used as a base address register in the auto-modification designation mode. When the copy valid flag indicates that the copy register has been written and when a value of the copy register identification code latch is consistent with a base address register number, the value of the copy register is supplied to the effective address calculation unit. <IMAGE>

IPC 1-7

G06F 9/38

IPC 8 full level

G06F 9/355 (2006.01); G06F 9/38 (2006.01)

CPC (source: EP US)

G06F 9/355 (2013.01 - EP US); G06F 9/3824 (2013.01 - EP US); G06F 9/383 (2013.01 - EP US)

Citation (search report)

• [X] EP 0155211 A2 19850918 - FUJITSU LTD [JP]
• [A] EP 0201833 A2 19861120 - HITACHI LTD [JP]
• [A] EP 0230038 A2 19870729 - NEC CORP [JP]
• [Y] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 31, no. 12, May 1989, NEW YORK US pages 321 - 322 'Base register buffer to eliminate address generation time in IBM system/370 architectures'
• [A] IBM TECHNICAL DISCLOSURE BULLETIN. vol. 23, no. 6, November 1980, NEW YORK US pages 2401 - 2403 ANGIULLI ET AL. 'Enhancements in implementing load address'

Designated contracting state (EPC)

DE FR GB

DOCDB simple family (publication)

EP 0443629 A2 19910828; EP 0443629 A3 19930728; EP 0443629 B1 19980909; DE 69130129 D1 19981015; DE 69130129 T2 19990506; US 5333288 A 19940726

DOCDB simple family (application)

EP 91102762 A 19910225; DE 69130129 T 19910225; US 66077991 A 19910225