EP 0449052 A3 19930224 - PARITY TEST METHOD AND APPARATUS FOR A MEMORY CHIP
Title (en)
PARITY TEST METHOD AND APPARATUS FOR A MEMORY CHIP
Publication
Application
Priority
US 50221290 A 19900329
Abstract (en)
[origin: EP0449052A2] A parity checking scheme for a memory device includes address parity checking. Parity checking is conducted on the input, before data is stored. At least one portion of parity checking, e.g., address parity checking, has selectable odd/even polarity and can be selectably disabled. The address parity signal and data parity signal are combined into an overall parity signal. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 11/10 (2006.01); G06F 12/16 (2006.01)
CPC (source: EP KR)
G06F 11/10 (2013.01 - KR); G06F 11/1016 (2013.01 - EP); G06F 11/1008 (2013.01 - EP)
Citation (search report)
- [X] EP 0185924 A2 19860702 - IBM [US]
- [X] EP 0084460 A2 19830727 - TANDEM COMPUTERS INC [US]
- [Y] IBM TECNICAL DISCLOSURE BULLETIN vol. 19, no. 3, August 1976, page 1019 J. H. DATRES, H. L. KURTZ 'Enhanced Error Detection for Storage Media'
- [A] PATENT ABSTRACTS OF JAPAN (P-488)(2297) 20 August 1986 & JP-A-61 070 638 ( TOSHIBA CORP. ) 11 April 1986
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0449052 A2 19911002; EP 0449052 A3 19930224; JP H04227549 A 19920817; KR 910017284 A 19911105
DOCDB simple family (application)
EP 91104000 A 19910315; JP 13372991 A 19910329; KR 910004861 A 19910328