EP 0452649 B1 19960619 - Interlocked on-chip ecc system
Title (en)
Interlocked on-chip ecc system
Title (de)
Verriegeltes On-Chip-Fehlererkennungs- und -korrektursystem
Title (fr)
Système détecteur et correcteur d'erreur sur puce à interverrouillage
Publication
Application
Priority
US 51789690 A 19900416
Abstract (en)
[origin: US5638385A] A memory device having an on-chip ECC system includes an array of memory cells, some of which have wider transistors than others so that they have faster access speeds. Data bits are written into ordinary memory cells and the check bits are written into the faster cells in order to make up for the delay associated with the calculation of the check bits.
IPC 1-7
IPC 8 full level
G06F 11/10 (2006.01); G06F 12/16 (2006.01); G11C 11/401 (2006.01); G11C 29/00 (2006.01); G11C 29/42 (2006.01)
CPC (source: EP US)
G06F 11/1008 (2013.01 - EP US); G06F 11/1076 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
US 5638385 A 19970610; DE 69120333 D1 19960725; DE 69120333 T2 19970123; EP 0452649 A2 19911023; EP 0452649 A3 19930224; EP 0452649 B1 19960619; JP 2571317 B2 19970116; JP H04222999 A 19920812; US 5307356 A 19940426
DOCDB simple family (application)
US 78562591 A 19911031; DE 69120333 T 19910301; EP 91103123 A 19910301; JP 5173291 A 19910315; US 51789690 A 19900416