EP 0458269 B1 19950308 - Phase-locked loop circuit.
Title (en)
Phase-locked loop circuit.
Title (de)
Phasenregelschleifenschaltung.
Title (fr)
Circuit de boucle d'asservissement de phase.
Publication
Application
Priority
JP 13154890 A 19900521
Abstract (en)
[origin: EP0458269A1] A phase-locked loop circuit comprises a controller (30) for driving a low-pass filter (18) continually in response to a signal from a phase comparator (14) which compares a divided frequency (fN) of an oscillation frequency (f0) with a reference frequency (fr). The low-pass filter supplies a control voltage (VT) having a changing rate higher than an ordinary rate to a voltage controlled oscillator (10) so that the divided frequency becomes equal to the reference frequency. Consequently, the lock-up time is sufficiently shortened, when a frequency dividing ratio (N) is changed. <IMAGE>
IPC 1-7
IPC 8 full level
H03L 7/089 (2006.01); H03L 7/107 (2006.01); H03L 7/187 (2006.01); H04H 20/00 (2008.01)
CPC (source: EP US)
H03L 7/0895 (2013.01 - EP US); H03L 7/1072 (2013.01 - EP US); H03L 7/187 (2013.01 - EP US); H04H 2201/13 (2013.01 - EP US)
Citation (examination)
Electronics Letters, vol.24, No.14, 7 July 1988, pages 880-882, "Digital PLL Lock-Detection Circuit"
Designated contracting state (EPC)
DE FR GB NL
DOCDB simple family (publication)
EP 0458269 A1 19911127; EP 0458269 B1 19950308; DE 69107891 D1 19950413; DE 69107891 T2 19951102; DE 69129946 D1 19980910; DE 69129946 T2 19990415; EP 0595787 A2 19940504; EP 0595787 A3 19940727; EP 0595787 B1 19980805; US 5220294 A 19930615
DOCDB simple family (application)
EP 91108195 A 19910521; DE 69107891 T 19910521; DE 69129946 T 19910521; EP 94100520 A 19910521; US 70325091 A 19910521