EP 0477989 A1 19920401 - Control processor for memory bus configuration.
Title (en)
Control processor for memory bus configuration.
Title (de)
Steuerprozessor für Speicherbuskonfiguration.
Title (fr)
Processeur de commande pour configuration de bus de mémoire.
Publication
Application
Priority
JP 26089190 A 19900928
Abstract (en)
A control processor (11) for memory bus configuration for a parallel computer enables a plural-to-one connection of the output buses (51-58) of plural processor elements (21-24, 31-34) to memory input bus (72) and input buses (61-68) of plural processor elements to memory output bus (73), and decreases the total number of memory buses, by means of a multiplexing unit (12) which multiplexes data on the output buses of plural processor elements and transfers the multiplexed data to the memory, a demultiplexing unit (13) which demultiplexes the multiplexed data delayed by the memory and transfers the demultiplexed data to the input buses of plural processor elements, and a program control unit (14) which controls the multiplex/demultiplex formats of the multiplexing unit and the demultiplexing unit. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 13/16 (2006.01); G06F 13/18 (2006.01); G06F 15/16 (2006.01); G06F 15/167 (2006.01)
CPC (source: EP)
G06F 13/1663 (2013.01); G06F 15/167 (2013.01)
Citation (search report)
- [Y] DE 3340123 A1 19850515 - HEIDTMANN KLAUS DR, et al
- [Y] WO 8704826 A1 19870813 - EASTMAN KODAK CO [US]
- [A] EP 0249720 A2 19871223 - IBM [US]
- [A] US 4164787 A 19790814 - ARANGUREN WILLIAM L [US]
- [A] EP 0228949 A2 19870715 - ITT [US]
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0477989 A1 19920401; EP 0477989 B1 19970611; DE 69126495 D1 19970717; DE 69126495 T2 19971204; JP H04137166 A 19920512
DOCDB simple family (application)
EP 91116697 A 19910930; DE 69126495 T 19910930; JP 26089190 A 19900928