EP 0514700 A3 19950111 -
Publication
Application
Priority
- GB 9111179 A 19910523
- GB 9127379 A 19911224
Abstract (en)
[origin: EP0514700A2] A circuit for a boundary-scan cell for the JTAG Architecture, the circuit including a capture section(50) coupled in cascade to an update section(52), and each section comprising a flip-flop (34,36)having a clock input for receiving a common clock signal (TCK, TCKB) and a multiplexer having a first input for receiving an input data signal, a second input coupled to an output of the flip-flop, an output coupled to a flip-flop input, and a select input for receiving a control signal for selectively coupling the first or second input to the multiplexer output. <IMAGE>
IPC 1-7
IPC 8 full level
G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G06F 11/22 (2006.01); G06F 17/50 (2006.01)
CPC (source: EP)
G01R 31/318541 (2013.01)
Citation (search report)
- [A] EP 0425416 A2 19910502 - IBM [US]
- [A] US 4504784 A 19850312 - GOEL PRABHAKAR [US], et al
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0514700 A2 19921125; EP 0514700 A3 19950111; EP 0514700 B1 19980729; DE 69226401 D1 19980903; DE 69226401 T2 19990304; JP 3207245 B2 20010910; JP H05180911 A 19930723
DOCDB simple family (application)
EP 92107369 A 19920430; DE 69226401 T 19920430; JP 15276792 A 19920520