EP 0520357 A3 19950405 - READ ONLY MEMORY DEVICE WITH RECHARGING TRANSISTOR AUTOMATICALLY SUPPLEMENTING CURRENT TO AN INPUT NODE OF OUTPUT INVERTER
Title (en)
READ ONLY MEMORY DEVICE WITH RECHARGING TRANSISTOR AUTOMATICALLY SUPPLEMENTING CURRENT TO AN INPUT NODE OF OUTPUT INVERTER
Publication
Application
Priority
JP 18309691 A 19910627
Abstract (en)
[origin: EP0520357A2] A read only memory device memorizes data bits by selectively providing current paths of n-channel enhancement type memory transistors (Qn11 to Qn13) between digit lines (Dl1 to DLn) and a ground voltage line, and one of the digit lines is coupled through an n-channel enhancement type transfer transistor of a column selector unit (12) with a drain node of a charging transistor (13) responsive to a control signal (CB), wherein the charging transistor is implemented by an n-channel enhancement type field effect transistor so that the drain node thereof is balanced with the selected digit line upon completion of a precharging phase, thereby preventing an output inverting circuit (14) coupled therewith from malfunction due to noise on the selected digit line. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 17/18 (2006.01); G11C 17/12 (2006.01)
CPC (source: EP US)
G11C 17/12 (2013.01 - EP US)
Citation (search report)
- [A] US 5022005 A 19910604 - TOHNISHI SHIGEJI [JP]
- [PA] US 5031148 A 19910709 - KITAZAWA SHOOJI [JP], et al
- [A] US 5022002 A 19910604 - IWAHASHI HIROSHI [JP]
- [A] US 5001668 A 19910319 - ITO MAKOTO [JP], et al
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0520357 A2 19921230; EP 0520357 A3 19950405; EP 0520357 B1 19970604; DE 69220144 D1 19970710; DE 69220144 T2 19980122; JP 3313383 B2 20020812; JP H056686 A 19930114; KR 950002728 B1 19950324; US 5274590 A 19931228
DOCDB simple family (application)
EP 92110515 A 19920622; DE 69220144 T 19920622; JP 18309691 A 19910627; KR 920011077 A 19920625; US 90168892 A 19920622