EP 0535395 A3 19940309 -
Publication
Application
Priority
JP 22324691 A 19910904
Abstract (en)
[origin: EP0535395A2] The present invention simplifies a partial multiplier selector for a multiplication circuit using the Booth Algorithm. For this purpose, a partial multiplier selector according to the present invention comprises a multiplier register (101) as a storing means to store multiplier data, a plurality of partial multiplier selecting units (102-105) as selection means comprising clocked inverters (106-125) which divide the multiplier data stored in the multiplier register (101) using the multiplication start signal and sequentially fetch them and control circuits (131-133) comprising latch circuits (201-204) which sequentially output the multiplication start signal to the partial multiplier selecting units (102-105) with a delay of one clock using the clock signal. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 7/00 (2006.01); G06F 7/52 (2006.01); G06F 7/523 (2006.01); G06F 7/533 (2006.01)
CPC (source: EP KR US)
G06F 7/52 (2013.01 - KR); G06F 7/5336 (2013.01 - EP US)
Citation (search report)
- [A] US 4972362 A 19901120 - ELKIND BOB [US], et al
- [A] US 4342984 A 19820803 - BERKE HERBERT, et al
- [A] IEE PROCEEDINGS E. COMPUTERS & DIGITAL TECHNIQUES vol. 136, no. 6, November 1989, STEVENAGE GB pages 517 - 523 BAYOUMI ET AL. 'Reconfigurable testable bit-serial multiplier for DSP applications'
Designated contracting state (EPC)
DE GB
DOCDB simple family (publication)
EP 0535395 A2 19930407; EP 0535395 A3 19940309; EP 0535395 B1 19981202; DE 69227744 D1 19990114; DE 69227744 T2 19990610; JP 2838924 B2 19981216; JP H0561648 A 19930312; KR 930006540 A 19930421; KR 950000388 B1 19950116; US 5337268 A 19940809
DOCDB simple family (application)
EP 92115195 A 19920904; DE 69227744 T 19920904; JP 22324691 A 19910904; KR 920016084 A 19920904; US 94031892 A 19920903