EP 0540119 A3 19931208 - MONOLITHIC DIGITAL PHASELOCK LOOP CIRCUIT
Title (en)
MONOLITHIC DIGITAL PHASELOCK LOOP CIRCUIT
Publication
Application
Priority
US 78484991 A 19911030
Abstract (en)
[origin: EP0540119A2] A monolithic phaselock loop circuit (PLL) for controlling the phase and frequency of a free-running oscillator to compensate for process induced variations in the VCO natural frequency and to extend the fpull-in range by +/-50% of the frequency of the reference clock. The PLL is comprised of a VCO, a digital phase comparator, a digital frequency divider and a digital sequential phase error detector (SPED). The SPED circuit comprises two up-down counters, one to control the phase; the other, the frequency; a first one-shot circuit to detect every level transition of the reference clock and a second one-shot circuit to provide a pulse for every falling edge of the reference clock; and a shift register to store the value of the phase comparator thereby providing indication of a frequency lock between the free running external oscillator and the VCO. <IMAGE>
IPC 1-7
IPC 8 full level
H03L 7/113 (2006.01); H03L 7/06 (2006.01); H03L 7/085 (2006.01); H03L 7/10 (2006.01)
CPC (source: EP US)
H03L 7/085 (2013.01 - EP US); H03L 7/113 (2013.01 - EP)
Citation (search report)
- [Y] EP 0402113 A2 19901212 - IBM [US]
- [X] US 4531102 A 19850723 - WHITLOCK JONATHAN B [US], et al
- [X] US 4975650 A 19901204 - MARTIN FREDERICK L [US]
- [A] US 4764737 A 19880816 - KAATZ GARY F [US]
- [A] FR 2600848 A1 19871231 - LABO CENT TELECOMMUNICAT [FR]
- [X] PATENT ABSTRACTS OF JAPAN vol. 13, no. 581 (E-865)21 December 1989 & JP-A-01 243 622 ( HITACHI LTD. ) 28 September 1989
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
US 5168245 A 19921201; EP 0540119 A2 19930505; EP 0540119 A3 19931208; JP 2771928 B2 19980702; JP H07264062 A 19951013
DOCDB simple family (application)
US 78484991 A 19911030; EP 92203320 A 19921028; JP 26605192 A 19921005