Global Patent Index - EP 0543257 A3

EP 0543257 A3 19940713 - METHOD OF MANUFACTURING A POWER-MISFET

Title (en)

METHOD OF MANUFACTURING A POWER-MISFET

Publication

EP 0543257 A3 19940713 (DE)

Application

EP 92119217 A 19921110

Priority

DE 4137341 A 19911113

Abstract (en)

[origin: EP0543257A2] A fabrication method for a low-voltage power MISFET is described, which method uses as few as three masks (photosteps). In the first step, a polysilicon layer (3) is patterned and a cell array and edge zones are produced. An oxide layer (2) is then applied which, in the second photostep, is opened above the cells and the edge zones and between the edge (4) and the cells. A metal layer is then applied which is broken by the third photostep between the cells and the edge (4). This produces magnetoresistors and channel stoppers (9). As a final step, a weakly conducting layer (20) is applied to the entire surface. <IMAGE>

IPC 1-7

H01L 21/336; H01L 29/06; H01L 29/784

IPC 8 full level

H01L 29/78 (2006.01); H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01)

CPC (source: EP US)

H01L 23/3171 (2013.01 - EP US); H01L 29/405 (2013.01 - EP US); H01L 29/66727 (2013.01 - EP US); H01L 29/7811 (2013.01 - EP US); H01L 29/0638 (2013.01 - EP US); H01L 29/402 (2013.01 - EP US); H01L 29/42376 (2013.01 - EP US); H01L 2924/0002 (2013.01 - EP US); Y10S 148/126 (2013.01 - EP US); Y10S 438/958 (2013.01 - EP US)

Citation (search report)

Designated contracting state (EPC)

DE FR GB IT

DOCDB simple family (publication)

DE 4137341 C1 19930429; EP 0543257 A2 19930526; EP 0543257 A3 19940713; JP 3267357 B2 20020318; JP H05243267 A 19930921; US 5302537 A 19940412

DOCDB simple family (application)

DE 4137341 A 19911113; EP 92119217 A 19921110; JP 32467392 A 19921111; US 97618992 A 19921113