EP 0576168 B1 19970402 - Digital phase locked loop
Title (en)
Digital phase locked loop
Title (de)
Digitaler Phasenregelkreis
Title (fr)
Boucle à verrouillage de phase numérique
Publication
Application
Priority
US 90436092 A 19920625
Abstract (en)
[origin: EP0576168A1] An improved digital phase locked loop (DPLL) has a fixed bandwidth independent of manufacturing and environmental variations. The DPLL bandwidth is optimized by monitoring (20) the delay propagation, i.e., the "silicon speed", of the module. This information is used by a bandwidth regulator to control the characteristics of the low pass filter (14) in the phase locked loop. The digital phase locked loop is also programmable to allow the user to control the phase shifting of the retiming clock. A phase shift control for a second, slave controlled oscillator (24) is used to retime the received data. This phase shift control allows the user to control the phase shifting of a retiming latch (28). <IMAGE>
IPC 1-7
IPC 8 full level
H03L 7/06 (2006.01); H03L 7/081 (2006.01); H03L 7/099 (2006.01); H04L 7/033 (2006.01)
CPC (source: EP US)
H03L 7/081 (2013.01 - EP US); H03L 7/0991 (2013.01 - EP US); H04L 7/0337 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
EP 0576168 A1 19931229; EP 0576168 B1 19970402; DE 69309349 D1 19970507; JP H06104742 A 19940415; JP H0795685 B2 19951011; US 5313503 A 19940517
DOCDB simple family (application)
EP 93304386 A 19930604; DE 69309349 T 19930604; JP 14446793 A 19930616; US 90436092 A 19920625