EP 0580085 B1 19980318 - Memory device component
Title (en)
Memory device component
Title (de)
Speicherbausteinanordnung
Title (fr)
Composant de dispositif de mémoire
Publication
Application
Priority
DE 4224421 A 19920724
Abstract (en)
[origin: EP0580085A2] A description is given of a level limit checking circuit for an electronic memory module (10a-10g; 10h) which has a memory logic (12a-12g) which combines bits of a supplied data stream (D1-D7), stored in a memory (11a-11g) of the electronic memory module (10a-10g), to form cells of a defined bit length. According to the invention it is proposed that the memory logic (12a-12g) generates for each complete cell a counting-pulse memory signal (CC1-CC7; CC), which is fed to a counting device (30a-30g) of the level limit-checking circuit (20), the counter reading of which is incremented by the generated counting-pulse memory signal (CC1-CC7; CC), that the level limit checking circuit (20) has an evaluation unit (40) which periodically inquires the counter reading of the counting device (30a-30g), and that the memory logic (12a-12g) generates after completion of a cell reading-out operation an acknowledgement memory signal (Q1-Q7; Q), which is fed to the counting device (30a-30g), the counter reading of which is decremented by the acknowledgement-pulse memory signal generated by the memory logic. <IMAGE>
IPC 1-7
IPC 8 full level
G11C 7/00 (2006.01)
CPC (source: EP)
G11C 7/00 (2013.01)
Designated contracting state (EPC)
AT BE CH DE ES FR GB IT LI NL SE
DOCDB simple family (publication)
EP 0580085 A2 19940126; EP 0580085 A3 19951220; EP 0580085 B1 19980318; AT E164256 T1 19980415; AU 4187693 A 19940127; AU 665428 B2 19960104; DE 4224421 A1 19940127; DE 59308271 D1 19980423; ES 2114976 T3 19980616
DOCDB simple family (application)
EP 93111417 A 19930716; AT 93111417 T 19930716; AU 4187693 A 19930713; DE 4224421 A 19920724; DE 59308271 T 19930716; ES 93111417 T 19930716