EP 0602806 A3 19941123 - High-level data link controller (HDLC) receiver.
Title (en)
High-level data link controller (HDLC) receiver.
Title (de)
HDLC-Empfänger.
Title (fr)
Récepteur HDLC.
Publication
Application
Priority
US 99257192 A 19921218
Abstract (en)
[origin: US5845085A] A high-level data-link controller (HDLC) receiver state machine for controlling the data-receiving functions of a HDLC receiver which receives frames of serialized data over a data-link. The state machine comprises a single logic device on an integrated circuit which is capable of determining in-frame status of received data, performing zero-deletions when the received data are in-frame, detecting abort signals within the received data, and controlling the overall functions of the receiver. The state machine may be utilized in a simplified HDLC receiver comprising the state machine, a shift register for converting serialized data into parallel data, a cyclical redundancy check (CRC) checker for validating the frames of received data, and a first-in, first-out (FIFO) buffer for storing the parallel data until the data are read by a controlling microprocessor.
IPC 1-7
IPC 8 full level
G06F 13/00 (2006.01); H04L 13/08 (2006.01); H04L 29/02 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01)
CPC (source: EP US)
H04L 9/40 (2022.05 - EP US); H04L 69/324 (2013.01 - EP US)
Citation (search report)
- [X] US 4974223 A 19901127 - ANCHETA TEOFILO C [US], et al
- [X] EP 0323222 A2 19890705 - NEC CORP [JP]
- [X] EP 0346555 A1 19891220 - IBM [US]
Designated contracting state (EPC)
BE DE DK ES FR GB GR IE IT LU NL PT SE
DOCDB simple family (publication)
US 5845085 A 19981201; DE 69330399 D1 20010809; DE 69330399 T2 20020502; EP 0602806 A2 19940622; EP 0602806 A3 19941123; EP 0602806 B1 20010704; JP H06237285 A 19940823
DOCDB simple family (application)
US 31680394 A 19941003; DE 69330399 T 19931123; EP 93309310 A 19931123; JP 31772093 A 19931217