EP 0607630 B1 19990317 - Circuit for delaying a useful signal
Title (en)
Circuit for delaying a useful signal
Title (de)
Schaltungsanordnung zum Verzögern eines Nutzsignals
Title (fr)
Circuit pour retarder un signal utile
Publication
Application
Priority
DE 4242201 A 19921215
Abstract (en)
[origin: DE4242201A1] The delay circuit stores discrete signal samples at intervals determined by a clock signal (CL) in sequence in a chain of memory elements to provide a predefined delay time. Each memory element operates a driving device. A shift register arrangement is formed from a chain of time-base circuits (20). Each driving device includes one of the time-base circuits. All time-base circuits are switched by the clock signal. A control arrangement supplies a start pulse to the first time-base circuit at a first time, t1. The start pulse is passed through the shift register arrangement until a second time, t2. The time between t1 and t2 is a selectable whole number of the period of the clock cycle. ADVANTAGE - Can be adapted, pref. switched, to provide multiple different delay times in simple way.
IPC 1-7
IPC 8 full level
G11C 19/00 (2006.01); G11C 27/04 (2006.01); H03H 11/26 (2006.01); H03H 17/08 (2006.01); H03K 5/13 (2006.01); H03K 5/133 (2014.01); H03K 5/135 (2006.01); H04N 5/46 (2006.01); H04N 9/81 (2006.01)
CPC (source: EP KR US)
G11C 19/00 (2013.01 - EP US); H03K 5/00 (2013.01 - KR); H03K 5/133 (2013.01 - EP US); H03K 5/135 (2013.01 - EP US); H04N 5/46 (2013.01 - EP US); H04N 9/81 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
DE 4242201 A1 19940616; DE 59309461 D1 19990422; EP 0607630 A1 19940727; EP 0607630 B1 19990317; JP H06237157 A 19940823; KR 100296208 B1 20011024; KR 940017157 A 19940726; US 5554949 A 19960910
DOCDB simple family (application)
DE 4242201 A 19921215; DE 59309461 T 19931210; EP 93203471 A 19931210; JP 31339393 A 19931214; KR 930027735 A 19931215; US 16726593 A 19931214