EP 0617376 A1 19940928 - Upgradeable data processing system.
Title (en)
Upgradeable data processing system.
Title (de)
Ausbaubares Datenverarbeitungssystem.
Title (fr)
Système améliorable de traitement des données.
Publication
Application
Priority
- CN 93102406 A 19930220
- US 8512593 A 19930630
Abstract (en)
A data processing system includes a first central processing unit (CPU), at least one expansion port into which additional CPUs may be inserted, and a system controller. Interrupt circuitry coupled to said first CPU, said at least one expansion port, and said system controller, is configured to allow the data processing system to operate as a multi-processor system, only one of the first and additional CPUs communicating with the system controller at any one time. <IMAGE>
IPC 1-7
IPC 8 full level
G06F 1/16 (2006.01); G06F 9/38 (2006.01); G06F 9/46 (2006.01); G06F 13/26 (2006.01); G06F 15/16 (2006.01); G06F 15/78 (2006.01)
CPC (source: EP KR US)
G06F 9/3879 (2013.01 - EP US); G06F 13/26 (2013.01 - EP US); G06F 15/16 (2013.01 - KR); G06F 15/7832 (2013.01 - EP US)
Citation (search report)
- [Y] US 3676861 A 19720711 - RUTH RICHARD LEROY [US]
- [A] EP 0411806 A2 19910206 - ADVANCED LOGIC RES INC [US]
- [PA] EP 0529142 A1 19930303 - ACER INC [TW]
- [Y] ANON.: "Dual Processor Boot Procedure for LAN Services", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 35, no. 3, August 1992 (1992-08-01), NEW YORK US, pages 306 - 316
- [A] PHILLIPS B.: "RISC Board Set Brings 20 MIPS per slot to VMEbus", ELECTRONIC DESIGN, vol. 37, no. 3, February 1989 (1989-02-01), HASBROUCK HEIGHTS, NEW JERSEY US, pages 95 - 97, XP000049660
- [A] PATENT ABSTRACTS OF JAPAN vol. 10, no. 282 (P - 500)<2338> 25 September 1986 (1986-09-25)
Designated contracting state (EPC)
DE FR GB NL
DOCDB simple family (publication)
EP 0617376 A1 19940928; JP H06301653 A 19941028; KR 940020230 A 19940915; US 5493655 A 19960220
DOCDB simple family (application)
EP 93114735 A 19930914; JP 31613993 A 19931216; KR 930019703 A 19930925; US 8512593 A 19930630