Global Patent Index - EP 0632492 A2

EP 0632492 A2 19950104 - Method of forming self-aligned LDD structures and low resistance contacts in thin film transistor technology devices.

Title (en)

Method of forming self-aligned LDD structures and low resistance contacts in thin film transistor technology devices.

Title (de)

Verfahren zur Bildung selbstausrichtender LDD-Strukturen und niederohmschen Kontakte für Anordnungen der Dünnschicht-Transistor-Technologie.

Title (fr)

Méthode pour former des structures LDD auto-alignées et des contacts de faible résistance dans des dispositifs de technologie transistor à couche mince.

Publication

EP 0632492 A2 19950104 (EN)

Application

EP 94304642 A 19940627

Priority

US 8529793 A 19930630

Abstract (en)

A prior art thin film transistor structure having a first and a second polycrystalline silicon layer of different conductivity types (P and N) has a high resistance contact at the resultant P-N junction. This contact resistance is reduced by forming TiSi2 (titanium disilicide) or other refractory metal silicides such as cobalt or molybdenum in specific regions, namely the P-N junction contact. Titanium disilicide consumes the portion of the second polycrystalline silicon layer in the P-N contact junction and at the same time consumes a small portion of the underlying first polycrystalline silicon layer, such that the high resistance P-N junction now no longer exists. The procedure to form low resistance contacts is extended to achieve a low leakage polysilicon TFT device. One or more LDD regions are formed to reduce the amount of leakage current of such transistor devices in an "OFF" state. The source/drain region(s) of the device are implanted with a first dopant type followed by an etch which forms spacers above the source/drain regions. Then, the source/drain regions are implanted with a second dopant type so that LDD regions are formed beneath the spacers. The electric field at the gate and source/drain boundaries of the device is spread over the entire LDD region, resulting in a lower peak electric field and hence less device leakage current. <IMAGE>

IPC 1-7

H01L 21/336; H01L 21/283; H01L 29/786; H01L 27/11; H01L 21/8244

IPC 8 full level

H01L 21/336 (2006.01); H01L 21/768 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10B 10/00 (2023.01)

CPC (source: EP)

H01L 21/76889 (2013.01); H01L 29/458 (2013.01); H01L 29/66765 (2013.01); H01L 29/78621 (2013.01); H10B 10/00 (2023.02); H10B 10/125 (2023.02)

Designated contracting state (EPC)

DE FR GB IT

DOCDB simple family (publication)

EP 0632492 A2 19950104; EP 0632492 A3 19961120; JP H07153968 A 19950616

DOCDB simple family (application)

EP 94304642 A 19940627; JP 14965394 A 19940630